Abstract: Devices and methods of fabricating integrated circuit devices for forming assymetric line/space with barrierless metallization are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, a dielectric matrix, and a hardmask, the dielectric matrix including a set of trenches etched into the dielectric matrix and a set of dielectric fins comprising the dielectric matrix, wherein the set of trenches and the set of dielectric fins are of equal width; damaging an inner surface of each trench of the set of trenches; etching the damaged material of the trenches removing the damaged material of the dielectric matrix; removing the hardmask; and metallizing the trenches by depositing a metal directly on the dielectric matrix with no barrier between the metal and the dielectric matrix after the etching. Also disclosed is an intermediate device formed by the method.

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects with improved adhesion are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a metal interconnect material directly over and contacting a top surface of the dielectric matrix, wherein the metal interconnect material fills the set of trenches and the set of vias; depositing a barrier layer over a top surface of the device; annealing the barrier layer to diffuse the barrier layer to a bottom surface of the metal interconnect material; planarizing a top surface of the intermediate semiconductor interconnect device; and depositing a dielectric cap over the intermediate semiconductor interconnect device.

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

Abstract: Described are dissolvable, porous solid structures formed using certain vinyl acetate-vinyl alcohol copolymers. The copolymer and the porosity of the structure allow for liquid flow during use such that the structure readily dissolves to provide a desired consumer experience. Also described are processes for making open cell foam and fibrous dissolvable solid structures.

Abstract: Embodiments of the disclosure include methods and compositions for the renewal of cardiomyocytes by targeting the Hippo pathway. In particular embodiments, an individual with a need for cardiomyocyte renewal is provided an effective amount of a shRNA molecule that targets the Sav1 gene. Particular shRNA sequences are disclosed.

Abstract: The present invention is directed to a personal care composition comprising from about 14% to about 40% of one or more surfactants; from about 0.1% to about 10% of one or more surfactant soluble agents having a C log P greater than 3.0; wherein when the personal care composition is diluted to about 1.5% surfactant concentration has a ratio of surfactant diffusion coefficient to soluble agent diffusion coefficient greater than 1.2.

Abstract: The present invention is directed to methods and compositions that provide therapy for at least one medical condition that directly or indirectly affects cardiac muscle cells (also known as cardiomyocytes) in a mammalian individual, including humans, dogs, cats, horse pigs, and so forth. The medical condition may be of any kind, including a cardiac condition such as heart failure, cardiomyopathy, myocardial infarction, and so forth. The medical condition may have a cardiac condition as its primary symptom or cause or it may be a secondary symptom or cause. The individual may be male or female and may be of any age.

Abstract: This invention relates to a foamable concentrated hair care composition comprising an anionic surfactant, a co-surfactant, a viscosity reducing agent, and a cationic polymer. The hair care composition may further comprise a silicone, wherein the silicone particle size is less than about 10 microns. The hair care composition has a viscosity of from about 1 to about 3,000 cps.

Abstract: A device includes a first dielectric material and a plurality of conductive lines disposed in the first dielectric material. Each of the plurality of conductive lines includes a conductive fill material and a liner layer disposed between at least a bottom surface of the conductive fill material and the first dielectric material. The first dielectric material defines at least one air gap between two of the plurality of conductive lines. The at least one air gap has a first depth greater than a second depth of the plurality of conductive lines.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes contacting a liner that is disposed adjacent to a porous interlayer dielectric (ILD) layer of dielectric material with a selectively reactive gas at reaction conditions. A portion of the liner is reacted with the selectively reactive gas to form a converted expanded portion that is disposed between a remaining portion of the liner and the porous ILD layer.

Abstract: In one example, a method includes forming a mask layer above or in a dielectric material. The dielectric material is exposed to photon radiation in an ambient atmosphere comprising a carbon gettering agent to generate damaged portions of the dielectric material. The mask layer blocks the photon radiation. The damaged portions of the dielectric material are removed.

Abstract: Embodiments of the present disclosure may provide methods of forming an IC structure with a pair of metal fins. An IC structure with a pair of metal fins can include two unitary metal fins positioned on a substrate and each including an elongated wire positioned on the substrate and a via positioned directly on a portion of the elongated wire, the elongated wire and the via of each unitary metal fin defining an inverted T-shape, wherein each unitary metal fin includes the elongated wire with a pair of opposing sidewalls substantially coplanar with a pair of opposing sidewalls of the via, and wherein the each unitary metal fin includes a single crystallographic orientation. An insulating layer can be positioned directly laterally between the two unitary metal fins.

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.

Abstract: At least one method, apparatus and system disclosed herein for forming an integrated circuit having a dual-orientation self aligned via. A first dielectric layer is formed on a semiconductor substrate. At least one first metal feature is formed in a first metal layer. A first cap feature is deposited over the first metal feature. A manganese silicate etch stop layer is formed above the dielectric layer. An etch process is performed for removing for at least removing the first cap feature. A second metal feature is formed in a second metal layer. A dual-orientation self aligned via connecting a portion of the second metal feature to the first metal feature is formed.

Abstract: Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit includes forming a first conductive interconnect line overlying a semiconductor substrate. The method forms an insulator cap defining a gap overlying the first conductive interconnect line. An upper interlayer dielectric material is deposited over the insulator cap and in the gap over the first conductive interconnect line. A via is etched through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line. The method deposits a conductive material into the via to form a conductive via in contact with the first conductive interconnect line.

Abstract: Described herein is a hair care composition having from about 0.2% to about 10% of one or more surfactant soluble active agents, from about 1% to about 10% of one or more viscosity reducing agents having a partition dispersion coefficient of from about 0.05 to about 2.0, from about 16% to about 40% of one or more anionic surfactants, and from about 40% to about 83% of a carrier. The hair care composition has a liquid phase kinematic viscosity, measured at 40 degrees Celsius, of from about 10 cSt to about 1000 cSt.

Abstract: Described herein is a hair care composition having from about 1% to about 10% of one or more viscosity reducing agents having a partition dispersion coefficient of from about 0.05 to about 5.1, from about 16% to about 40% of one or more anionic surfactants, and from about 40% to about 83% of a carrier. The hair care composition has a liquid phase kinematic viscosity, measured at 40 degrees Celsius, of from about 10 cSt to about 500 cSt.

Abstract: This invention relates to a foamable hair care composition comprising an anionic surfactant, a co-surfactant, a viscosity reducing agent, and a cationic polymer having a weight average molecular weight of less than about 1,000,000 g/mol. The hair care composition may further comprise a silicone, wherein the silicone particle size is less than about 10 microns. The hair care composition has a viscosity of from about 1 to about 3,000 cps.

Abstract: Described herein is a hair care composition having from about 1% to about 10% of one or more viscosity reducing agents having a partition dispersion coefficient of from about ?3.1 to about ?0.7, from about 16% to about 40% of one or more anionic surfactants, and from about 40% to about 83% of a carrier. The hair care composition has a liquid phase kinematic viscosity, measured at 40 degrees Celsius, of from about 10 cSt to about 500 cSt.