Patents by Inventor Todd Ryan

Todd Ryan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS FOR PRODUCING INTEGRATED CIRCUITS WITH AN INSULTATING LAYER
    Publication number: 20150340274
    Abstract: Methods for producing integrated circuits are provided. A method for producing an integrated circuit includes forming an insulating layer overlying a substrate, where the insulating layer is formed within a trench. The insulating layer is infused with water, and the insulating layer is annealed while being irradiated. The insulating layer is annealed at a dry anneal temperature of about 800 degrees centigrade or less.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 26, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Errol Todd Ryan, Sukwon Hong
  • Compositions in the Form of Dissolvable Solid Structures
    Publication number: 20150315350
    Abstract: Described are dissolvable, porous solid structures formed using certain vinyl acetate-vinyl alcohol copolymers. The copolymer and the porosity of the structure allow for liquid flow during use such that the structure readily dissolves to provide a desired consumer experience. Also described are processes for making open cell foam and fibrous dissolvable solid structures.
    Type: Application
    Filed: April 20, 2015
    Publication date: November 5, 2015
    Inventors: Min MAO, Mark William HAMERSKY, Robert Wayne GLENN, JR., Todd Ryan THOMPSON
  • METHOD TO ETCH CU/TA/TAN SELECTIVELY USING DILUTE AQUEOUS HF/HCL SOLUTION
    Publication number: 20150255340
    Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 10, 2015
    Applicants: GLOBALFOUNDRIES, Inc., Intermolecular Inc.
    Inventors: Anh Duong, Errol Todd Ryan
  • Method to etch Cu/Ta/TaN selectively using dilute aqueous HF/HCI solution
    Patent number: 9123785
    Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: September 1, 2015
    Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, INC.
    Inventors: Anh Duong, Errol Todd Ryan
  • Methods for fabricating integrated circuits using surface modification to selectively inhibit etching
    Patent number: 9076846
    Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first exposed surface including an elemental metal material and a second exposed surface including a barrier material. The elemental metal material has a first etch rate when exposed to a wet etchant and the barrier material has a second etch rate when exposed to the wet etchant. Further, the method includes modifying the first exposed surface to form a modified first exposed surface so as to reduce the first etch rate when exposed to the wet etchant and applying the wet etchant simultaneously to the modified first exposed surface and to the second exposed surface.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: July 7, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Errol Todd Ryan, Kunaljeet Tanwar, Xunyuan Zhang
  • Methods for integration of pore stuffing material
    Patent number: 9054052
    Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: June 9, 2015
    Assignee: GLOBAL FOUNDRIES INC.
    Inventors: Nicholas Vincent Licausi, Errol Todd Ryan, Ming He, Moosung M. Chae, Kunaljeet Tanwar, Larry Zhao, Christian Witt, Ailian Zhao, Sean X. Lin, Xunyuan Zhang
  • Advanced low k cap film formation process for nano electronic devices
    Patent number: 9040411
    Abstract: A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: May 26, 2015
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Alfred Grill, Joshua L. Herman, Son Nguyen, E. Todd Ryan, Hosadurga K. Shobha
  • method to etch cu/Ta/TaN selectively using dilute aqueous Hf/h2so4 solution
    Publication number: 20150130065
    Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H2SO4 can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicants: Intermolecular Inc.
    Inventors: Anh Duong, Errol Todd Ryan
  • METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SURFACE MODIFICATION TO SELECTIVELY INHIBIT ETCHING
    Publication number: 20150126028
    Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first exposed surface including an elemental metal material and a second exposed surface including a barrier material. The elemental metal material has a first etch rate when exposed to a wet etchant and the barrier material has a second etch rate when exposed to the wet etchant. Further, the method includes modifying the first exposed surface to form a modified first exposed surface so as to reduce the first etch rate when exposed to the wet etchant and applying the wet etchant simultaneously to the modified first exposed surface and to the second exposed surface.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Applicant: GLOBALFOUNDRIES, Inc
    Inventors: Errol Todd Ryan, Kunaljeet Tanwar, Xunyuan Zhang
  • Selective etching of copper and copper-barrier materials by an aqueous base solution with fluoride addition
    Patent number: 9012322
    Abstract: Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very little effect on nearby oxides (e.g., silicon dioxide hard mask materials), and etching refractory metals (e.g. tantalum) at an intermediate rate. The solutions are aqueous base solutions (e.g., ammonia-peroxide mixture or TMAH-peroxide mixture) with just enough hydrofluoric acid (HF) added to make the solution's pH about 8-10. Applications include metallization of sub-micron logic structures.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Anh Duong, Errol Todd Ryan
  • Barrier layer conformality in copper interconnects
    Patent number: 8980740
    Abstract: A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: March 17, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Errol Todd Ryan, Xunyuan Zhang
  • Compositionally-graded and structurally-graded photovoltaic devices and methods of fabricating such devices
    Patent number: 8962978
    Abstract: A semiconductor structure is described, including a semiconductor substrate and a semiconductor layer disposed on the semiconductor substrate. The semiconductor layer is both compositionally graded and structurally graded. Specifically, the semiconductor layer is compositionally graded through its thickness from substantially intrinsic at the interface with the substrate to substantially doped at an opposite surface. Further, the semiconductor layer is structurally graded through its thickness from substantially crystalline at the interface with the substrate to substantially amorphous at the opposite surface. Related methods are also described.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: February 24, 2015
    Assignee: General Electric Company
    Inventors: Bastiaan Arie Korevaar, James Neil Johnson, Todd Ryan Tolliver, Theodore Carlton Kreutz, Xiaolan Zhang
  • Methods of self-forming barrier integration with pore stuffed ULK material
    Patent number: 8932934
    Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: January 13, 2015
    Assignee: Global Foundries Inc.
    Inventors: Moosung M. Chae, Errol Todd Ryan, Nicholas Vincent Licausi, Christian Witt, Ailian Zhao, Ming He, Sean X. Lin, Xunyuan Zhang, Kunaljeet Tanwar
  • METHODS OF FORMING COPPER-BASED NITRIDE LINER/PASSIVATION LAYERS FOR CONDUCTIVE COPPER STRUCTURES AND THE RESULTING DEVICE
    Publication number: 20140361435
    Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.
    Type: Application
    Filed: August 27, 2014
    Publication date: December 11, 2014
    Inventors: Xunyuan Zhang, Larry Zhao, Ming He, Sean Lin, John Iacoponi, Errol Todd Ryan
  • METHODS FOR INTEGRATION OF PORE STUFFING MATERIAL
    Publication number: 20140353802
    Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas Vincent LICAUSI, Errol Todd RYAN, Ming HE, Moosung M. CHAE, Kunaljeet TANWAR, Larry ZHAO, Christian WITT, Ailian ZHAO, Sean X. LIN, Xunyuan ZHANG
  • METHODS OF SEMICONDUCTOR CONTAMINANT REMOVAL USING SUPERCRITICAL FLUID
    Publication number: 20140353805
    Abstract: A process is provided for the removal of contaminants from a semiconductor device, for example, removing contaminants from pores of an ultra-low k film. In one aspect, a method includes: providing a dielectric layer with contaminant-containing pores and exposing the dielectric layer to a supercritical fluid. The supercritical fluid can dissolve and remove the contaminants. In another aspect, an intermediate semiconductor device structure is provided that contains a dielectric layer with contaminant-containing pores and a supercritical fluid within the pores. In another aspect, a semiconductor device structure with a dielectric layer containing uncontaminated pores is provided.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Errol Todd RYAN, Moosung M. CHAE, Larry ZHAO, Kunaljeet TANWAR, Nicholas Vincent LICAUSI, Christian WITT, Ailian ZHAO, Ming HE, Sean X. LIN, Xunyuan ZHANG
  • METHODS OF SELF-FORMING BARRIER INTEGRATION WITH PORE STUFFED ULK MATERIAL
    Publication number: 20140353835
    Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Inventors: Moosung M. CHAE, Errol Todd RYAN, Nicholas Vincent LICAUSI, Christian WITT, Ailian ZHAO, Ming HE, Sean X. LIN, Xunyuan ZHANG, Kunaljeet TANWAR
  • Methods of forming conductive structures using a sacrificial liner layer
    Patent number: 8889549
    Abstract: One illustrative method disclosed herein includes performing a first etching process to define a via opening in a layer of insulating material, performing at least one process operation to form a sacrificial liner layer on the sidewalls of the via opening, performing a second etching process to define a trench in the layer of insulating material, wherein the sacrificial liner layer is exposed to the second etching process, after performing the second etching process, performing a third etching process to remove the sacrificial liner layer and, after performing the third etching process, forming a conductive structure in at least the via opening and the trench.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: November 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Nicholas V. LiCausi, Errol Todd Ryan
  • Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
    Patent number: 8859419
    Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: October 14, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Larry Zhao, Ming He, Sean Lin, John Iacoponi, Errol Todd Ryan
  • Selective etching of copper and copper-barrier materials by an aqueous base solution with fluoride addition
    Publication number: 20140302671
    Abstract: Wet-etch solutions for conductive metals (e.g., copper) and metal nitrides (e.g., tantalum nitride) can be tuned to differentially etch the conductive metals and metal nitrides while having very little effect on nearby oxides (e.g., silicon dioxide hard mask materials), and etching refractory metals (e.g. tantalum) at an intermediate rate. The solutions are aqueous base solutions (e.g., ammonia-peroxide mixture or TMAH-peroxide mixture) with just enough hydrofluoric acid (HF) added to make the solution's pH about 8-10. Applications include metallization of sub-micron logic structures.
    Type: Application
    Filed: April 5, 2013
    Publication date: October 9, 2014
    Applicant: Intermolecular Inc.
    Inventors: Anh Duong, Errol Todd Ryan