Patents by Inventor Todd Ryan

Todd Ryan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HIPPO AND DYSTROPHIN COMPLEX SIGNALING IN CARDIOMYOCYTE RENEWAL
    Publication number: 20160312219
    Abstract: The present invention is directed to methods and compositions that provide therapy for at least one medical condition that directly or indirectly affects cardiac muscle cells (also known as cardiomyocytes) in a mammalian individual, including humans, dogs, cats, horse pigs, and so forth. The medical condition may be of any kind, including a cardiac condition such as heart failure, cardiomyopathy, myocardial infarction, and so forth. The medical condition may have a cardiac condition as its primary symptom or cause or it may be a secondary symptom or cause. The individual may be male or female and may be of any age.
    Type: Application
    Filed: December 9, 2014
    Publication date: October 27, 2016
    Inventors: James F MARTIN, Yuka MORIKAWA, Todd Ryan HEALLEN, John LEACH
  • DELIVERY OF SURFACTANT SOLUBLE ANTI-DANDRUFF AGENT
    Publication number: 20160310393
    Abstract: A hair care composition directed to from about 14% to about 40% of one or more surfactants; from about 0.1% to 10% of one or more surfactant soluble antidandruff agents; wherein when the hair care composition is diluted to 1.3% surfactant concentration has a ratio of surfactant diffusion coefficient to soluble agent diffusion coefficient less than 0.6 or greater than 1.4.
    Type: Application
    Filed: April 22, 2016
    Publication date: October 27, 2016
    Inventors: Debora W. Chang, Eric Scott Johnson, Robert Wayne Glenn, JR., Todd Ryan Thompson, Allison Lynn Edwards, Michelle Lynn Carter
  • LOW VISCOSITY HAIR CARE COMPOSITION
    Publication number: 20160310402
    Abstract: This invention relates to a foamable concentrated hair care composition comprising an anionic surfactant, a co-surfactant, a viscosity reducing agent, and a cationic polymer. The hair care composition may further comprise a silicone, wherein the silicone particle size is less than about 10 microns. The hair care composition has a viscosity of from about 1 to about 3,000 cps.
    Type: Application
    Filed: April 22, 2016
    Publication date: October 27, 2016
    Inventors: Jean Jianqun Zhao, Robert Wayne Glenn, JR., Todd Ryan Thompson, Jazmin Veronica Torres Rivera, III, Sarah Elizabeth Mullen, Howard David Hutton, III, Peter Herbert Koenig, David Michael Eike
  • Methods of forming an improved via to contact interface by selective formation of a metal silicide capping layer
    Patent number: 9466530
    Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Tibor Bolom, Errol Todd Ryan
  • INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SELF-ALIGNED VIAS
    Publication number: 20160254185
    Abstract: Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit includes forming a first conductive interconnect line overlying a semiconductor substrate. The method forms an insulator cap defining a gap overlying the first conductive interconnect line. An upper interlayer dielectric material is deposited over the insulator cap and in the gap over the first conductive interconnect line. A via is etched through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line. The method deposits a conductive material into the via to form a conductive via in contact with the first conductive interconnect line.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Inventors: Errol Todd Ryan, Sean X. Lin
  • Methods of producing integrated circuits with an air gap
    Patent number: 9431294
    Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: August 30, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Ming He, Errol Todd Ryan, Roderick Alan Augur, Craig Child, Larry Zhao
  • METHOD FOR RECESSING A CARBON-DOPED LAYER OF A SEMICONDUCTOR STRUCTURE
    Publication number: 20160163559
    Abstract: Semiconductor structure and methods of fabrication thereof are provided which includes, for instance, providing a carbon-doped material layer within a recess of a semiconductor structure; removing, in part, carbon from the carbon-doped material layer to obtain, at least in part, a carbon-depleted region thereof, the carbon-depleted region having a modified etch property with an increased etch rate compared to an etch rate of the carbon-doped material layer; and recessing the carbon-depleted region of the carbon-doped material layer by an etching process, with the carbon-depleted region being recessed based upon, in part, the modified etch property of the carbon-depleted region.
    Type: Application
    Filed: July 29, 2015
    Publication date: June 9, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Errol Todd RYAN
  • Method for defining an isolation region(s) of a semiconductor structure
    Patent number: 9349631
    Abstract: Methods for defining an isolation region of a semiconductor structure are provided. The method includes, for instance: providing a semiconductor structure with a recess therein; disposing an insulator layer conformally within the recess in the semiconductor structure to partially fill the recess; modifying at least one material property of the insulator layer to obtain a densified insulator layer within the recess, where the modifying reduces a thickness of the densified insulator layer compared to that of the insulator layer; and depositing at least one additional insulator layer within the recess over the densified insulator layer, where the densified insulator layer within the recess defines, at least in part, an isolation region of the semiconductor structure.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Errol Todd Ryan
  • Method to etch Cu/Ta/TaN selectively using dilute aqueous HF/HSOsolution
    Patent number: 9343408
    Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H2SO4 can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: May 17, 2016
    Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, Inc.
    Inventors: Anh Duong, Errol Todd Ryan
  • METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A METAL SILICIDE CAPPING LAYER
    Publication number: 20160126135
    Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 5, 2016
    Inventors: Xunyuan Zhang, Tibor Bolom, Errol Todd Ryan
  • METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A CONDUCTIVE CAPPING LAYER
    Publication number: 20160126190
    Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.
    Type: Application
    Filed: October 29, 2014
    Publication date: May 5, 2016
    Inventors: Xunyuan Zhang, Tibor Bolom, Errol Todd Ryan
  • INTEGRATED CIRCUITS WITH AN AIR GAP AND METHODS OF PRODUCING THE SAME
    Publication number: 20160118292
    Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 28, 2016
    Inventors: Ming He, Errol Todd Ryan, Roderick Alan Augur, Craig Child, Larry Zhao
  • Copper based nitride liner passivation layers for conductive copper structures
    Patent number: 9318436
    Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 19, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Larry Zhao, Ming He, Sean Lin, John Iacoponi, Errol Todd Ryan
  • METHOD FOR DEFINING AN ISOLATION REGION(S) OF A SEMICONDUCTOR STRUCTURE
    Publication number: 20160099168
    Abstract: Methods for defining an isolation region of a semiconductor structure are provided. The method includes, for instance: providing a semiconductor structure with a recess therein; disposing an insulator layer conformally within the recess in the semiconductor structure to partially fill the recess; modifying at least one material property of the insulator layer to obtain a densified insulator layer within the recess, where the modifying reduces a thickness of the densified insulator layer compared to that of the insulator layer; and depositing at least one additional insulator layer within the recess over the densified insulator layer, where the densified insulator layer within the recess defines, at least in part, an isolation region of the semiconductor structure.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 7, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Errol Todd RYAN
  • ANISOTROPIC MATERIAL DAMAGE PROCESS FOR ETCHING LOW-K DIELECTRIC MATERIALS
    Publication number: 20160020140
    Abstract: In one example, a method includes forming a mask layer above or in a dielectric material. The dielectric material is exposed to photon radiation in an ambient atmosphere comprising a carbon gettering agent to generate damaged portions of the dielectric material. The mask layer blocks the photon radiation. The damaged portions of the dielectric material are removed.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 21, 2016
    Inventor: Errol Todd Ryan
  • Personal care composition in the form of a dissolvable article
    Patent number: 9233055
    Abstract: An article that is a porous, dissolvable solid structure that dissolves easily due to the shape, product orientation and/or method of manufacturing the porous, dissolvable solid structure. The process of making the Article involves preparing a pre-mixture, aerating the pre-mixture, dosing the pre-mixture into individual cavities in molds, and drying the pre-mixture to an Article having an open celled foam with a % open cell of from about 80% to about 100%.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: January 12, 2016
    Assignee: The Procter & Gamble Company
    Inventors: Robert Wayne Glenn, Jr., Eric Paul Granberg, Lynn Kristin Stechschulte, Matthew Steven Ritter, Jason Donald McCarty, Michael Edward Thomas, Todd Ryan Thompson, Jay Ryan Tenkman, Emily Ragland Muszynski, Dale Francis Bittner, Nathan Alan Gill
  • Method to etch cu/Ta/TaN selectively using dilute aqueous Hf/hCl solution
    Patent number: 9224639
    Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: December 29, 2015
    Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, INC.
    Inventors: Anh Duong, Errol Todd Ryan
  • INTEGRATED CIRCUITS INCLUDING MODIFIED LINERS AND METHODS FOR FABRICATING THE SAME
    Publication number: 20150371898
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes contacting a liner that is disposed adjacent to a porous interlayer dielectric (ILD) layer of dielectric material with a selectively reactive gas at reaction conditions. A portion of the liner is reacted with the selectively reactive gas to form a converted expanded portion that is disposed between a remaining portion of the liner and the porous ILD layer.
    Type: Application
    Filed: June 23, 2014
    Publication date: December 24, 2015
    Inventors: ERROL TODD RYAN, Xunyuan Zhang
  • Method of Treating Hair with a Concentrated Conditioner
    Publication number: 20150359728
    Abstract: A method of treating the hair including providing a pre-aerated concentrated hair care composition. The pre-aerated concentrated hair care composition includes one or more silicones, perfume, and from about 2% to about 10% high melting point fatty compounds. The method also includes applying the pre-aerated concentrated hair care composition the hair; and rinsing the pre-aerated concentrated hair care composition from the hair. The pre-aerated concentrated hair care composition has a density of from about 0.15 g/cm3 to about 0.75 g/cm3 when dispensed from the aerosol foam dispenser.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 17, 2015
    Inventors: Robert Wayne GLENN, JR., Kathleen Mary KAUFMAN, Dariush HOSSEINPOUR, Todd Ryan THOMPSON
  • Method to etch cu/Ta/TaN selectively using dilute aqueous Hf/hCl solution
    Publication number: 20150348833
    Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
    Type: Application
    Filed: July 23, 2015
    Publication date: December 3, 2015
    Inventors: Anh Duong, Errol Todd Ryan