Abstract: A signal processing device includes a data writing unit, a channel number converting unit, and a plurality of serial data transferring unit. The data writing unit is configured to write data of m channels into a memory. The channel number converting unit is configured to output the data read from the memory as data of n channels, where m is larger than n. The plurality of serial data transferring unit is configured to transfer the data of the n channels to a processing device in a subsequent stage.

Abstract: A signal processing device includes a data writing unit, a channel number converting unit, and a plurality of serial data transferring unit. The data writing unit is configured to write data of m channels into a memory. The channel number converting unit is configured to output the data read from the memory as data of n channels, where m is larger than n. The plurality of serial data transferring unit is configured to transfer the data of the n channels to a processing device in a subsequent stage.

Abstract: A semiconductor integrated circuit includes a plurality of processing circuits including a sample and hold circuit, and a timing signal generation circuit that receives a reference clock signal and generates a timing signal to control a timing to operate the sample and hold circuit based on the reference clock signal. The plurality of processing circuits serially execute processing in order from the processing circuit at a preceding stage to the processing circuit at a subsequent stage. The timing signal generation circuit is coupled to the plurality of processing circuits so as to supply the timing signal to each of the plurality of processing circuits in order from the processing circuit at the subsequent stage to the processing circuit at the preceding stage.

Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.

Abstract: A solid-state imaging device includes a photoelectric converter including a plurality of light receiving elements arranged along one direction in correspondence with each color of received light/each light receiving element generating an electric charge corresponding to an amount of received light, an electric charge storage unit including a plurality of capacitors storing the electric charges generated by the respective light receiving elements, and a signal processing unit configured to process each of the electric charges stored by the plurality of capacitors as a signal. The electric charge storage unit is disposed so as to oppose the signal processing unit across the photoelectric converter.

Abstract: A semiconductor integrated circuit includes a first power supply line, a second power supply line, and a voltage supplied circuit. The first power supply line is connected to a voltage supply source. The second power supply line is connected to the first power supply line at a connection point connecting a first point of the first power supply line and a second point of the second power supply line. The second point is included in a portion of the second power supply line excluding end portions of the second power supply line. The voltage supplied circuit is connected to the second power supply line.

Abstract: A photoelectric conversion device includes a pixel block including a plurality of pixels, a signal generating block, and a signal processing block. Each of the plurality of pixels includes a photoelectric conversion element to photoelectrically convert light striking the photoelectric conversion element into pixel data and output the pixel data; and a reset unit to reset electrical charge of the photoelectrically converted pixel data light and output a reset signal. The signal generating block includes a reference signal generator to generate a reference signal. The signal processing block performs correlated double sampling (CDS) on the reference signal to obtain correction data, and perform CDS on the pixel data and the reset signal to generate an output signal to correct the output signal with the correction data.

Abstract: A solid-state image sensor includes a pixel unit having a plurality of pixels arranged in matrix, a read signal processing circuit, a test signal output circuit, a test signal generating circuit, and a control circuit that controls operations of the above mentioned circuits. Each of the plurality of pixels outputs a pixel signal that is obtained by amplifying a photoelectrically converted signal using an output amplifier in one or more pixel units. The read signal processing circuit reads the pixel signal output from the pixel unit in units of one or more pixels to a corresponding signal line and processes the pixel signal. The test signal output circuit, having a test output amplifier for each signal line, outputs a signal from the test output amplifier to the signal line in response to a test signal input to the test output amplifier. The test signal generating circuit generates the test signal.

Abstract: A photoelectric conversion device, having a horizontally long rectangular shape, includes a pixel block including pixels; signal processing blocks, arranged along a transverse direction of the photoelectric conversion device, for processing a pixel signal; a power source voltage supply block for supplying a power source voltage. The pixel includes a photoelectric conversion element for performing a photoelectric conversion, and a charge/voltage conversion unit, including a first amplifier, for converting the converted charge into a voltage. In the pixel block, columns are arranged in a longitudinal direction. Each column is set as a unit of signal processing including a predetermined number of pixels. Vertical power feeding wirings for feeding the power source voltage to the columns of the pixel block, from the transverse direction, are arranged.

Abstract: An analog signal bus driving circuit includes a plurality of signal sources, a plurality of signal output amplifiers, a plurality of shield drive amplifiers, and a time-division control circuit. The plurality of signal sources generate a plurality of analog signals. The plurality of signal output amplifiers output the plurality of analog signals to at least one signal line. The plurality of shield drive amplifiers output the plurality of analog signals to a shield line. The shield line extends along the at least one signal line to at least partially surround the at least one signal line. The time-division control circuit sequentially drives the plurality of signal output amplifiers in a time-division manner to sequentially output the plurality of analog signals in a time-division manner from the plurality of signal sources to the at least one signal line.

Abstract: A semiconductor integrated circuit includes a first power supply line, a second power supply line, and a voltage supplied circuit. The first power supply line is connected to a voltage supply source. The second power supply line is connected to the first power supply line at a connection point connecting a first point of the first power supply line and a second point of the second power supply line. The second point is included in a portion of the second power supply line excluding end portions of the second power supply line. The voltage supplied circuit is connected to the second power supply line.

Abstract: A semiconductor integrated circuit including a differential amplifier circuit, a first output circuit, a second output circuit, a selection circuit, and a feedback circuit. The differential amplifier circuit is configured to operate at a first source voltage. The first output circuit is configured to receive an output of the differential amplifier circuit, output a first output, and operate at the first source voltage. The second output circuit is configured to receive an output of the differential amplifier circuit, output a second output, and operate at a second source voltage lower than the first source voltage. The selection circuit is configured to select one of the first output from the first output circuit and the second output from the second output circuit according to an operating phase determined by an external control signal. The feedback circuit is connected between the differential amplifier circuit and the selection circuit.

Abstract: A solid-state imaging device includes a photoelectric converter including a plurality of light receiving elements arranged along one direction in correspondence with each color of received light/each light receiving element generating an electric charge corresponding to an amount of received light, an electric charge storage unit including a plurality of capacitors storing the electric charges generated by the respective light receiving elements, and a signal processing unit configured to process each of the electric charges stored by the plurality of capacitors as a signal. The electric charge storage unit is disposed so as to oppose the signal processing unit across the photoelectric converter.

Abstract: An image capturing device includes a photoelectric converter including one of a plurality of pixels, an amplifier, and control circuitry. Each pixel includes at least a photoelectric conversion element, and is configured to output an electrical signal corresponding to an intensity of light received by the photoelectric conversion element. The control circuitry is configured to sequentially drive the plurality of pixels in a time staggered manner such that, during a time from when a certain pixel outputs a reset signal of the certain pixel to the amplifier to when the pixel outputs a signal of the certain pixel to the amplifier, a subsequent pixel of the certain pixel outputs one of a reset signal and a signal of the subsequent pixel to the amplifier. The reset signal represents an electrical signal of a reset voltage to reset a corresponding pixel. The signal represents the electrical signal.

Abstract: A solid-state imaging device includes a photoelectric converter including a plurality of light receiving elements arranged along one direction in correspondence with each color of received light, each light receiving element generating an electric charge corresponding to an amount of received light, an electric charge storage unit including a plurality of capacitors storing the electric charges generated by the respective light receiving elements, and a signal processing unit configured to process each of the electric charges stored by the plurality of capacitors as a signal. The electric charge storage unit is disposed so as to oppose the signal processing unit across the photoelectric converter.

Abstract: A photoelectric conversion device includes a pixel array including one or more linear array, each including plural linearly-arranged pixels; and plural memory circuits, each including plural memory cells. The plural pixels in the pixel array are connected one-to-one to the plural memory cells of the plural memory circuits. Each of the plural pixels alternately outputs a photoelectric conversion value indicating an electric voltage generated in accordance with a light amount of an incident light entering the pixel, and a reset value indicating a reference charge of the pixel, to the memory cell corresponding to the pixel. Each of the plural memory cells temporarily stores the photoelectric conversion value and the reset value output from the pixel corresponding to the memory cell. Each of the plural memory circuits outputs the photoelectric conversion values and the reset values stored in the plural memory cells of the memory circuit, in a predetermined order.

Abstract: A semiconductor integrated circuit includes a plurality of processing circuits including a sample and hold circuit, and a timing signal generation circuit that receives a reference clock signal and generates a timing signal to control a timing to operate the sample and hold circuit based on the reference clock signal. The plurality of processing circuits serially execute processing in order from the processing circuit at a preceding stage to the processing circuit at a subsequent stage. The timing signal generation circuit is coupled to the plurality of processing circuits so as to supply the timing signal to each of the plurality of processing circuits in order from the processing circuit at the subsequent stage to the processing circuit at the preceding stage.

Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.

Abstract: A solid-state imaging device includes: a valid area including pixels that are not shielded from light; a first light-blocked area and a second light-blocked area each including pixels that are shielded from light; an analog-to-digital converting unit to convert the electric charge accumulated by the pixels belonging to the first light-blocked area, the valid area, and the second light-blocked area, to image data at a time; a signal reading unit to read light-blocked data obtained from the first light-blocked area and the second light-blocked area, and valid data obtained from the valid area, in units of pixels; a reference black level estimating unit to estimate a reference black level of the light-blocked data; and a level correction unit to correct, based on the estimated reference black level, a size of the valid data obtained simultaneously with the light-blocked data used in estimating the reference black level.

Abstract: An imaging device includes a pixel region in which a plurality of pixels and a plurality of charge-to-voltage conversion circuits are arranged in matrix. The pixels include photoelectric conversion elements that output charges in accordance with intensity of received light. The charge-to-voltage conversion circuits convert the charges output from the pixels into voltage signals. The pixel region includes an isolated region including isolated shaded pixels covered with a first shading metal of the same layer as a layer of wiring metals of the charge-to-voltage conversion circuits, and an isolated pixel that is not covered with the metal. All the pixels surrounding the isolated pixel in the isolated region are the isolated shaded pixels.