Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.

Abstract: An imaging device includes a plurality of arranged imaging elements each including: a light-receiving element configured to generate charge from received light by photoelectric conversion, a floating diffusion configured to convert the charge generated by the light-receiving element into voltage, a charge transfer switch configured to transfer the charge from the light-receiving element to the floating diffusion, a reset switch configured to reset the voltage of the floating diffusion, and a source follower configured to amplify the voltage of the floating diffusion. The reset switch is configured to reset the voltage of the floating diffusion a plurality of times for each of predetermined pixel groups in a single image data acquisition period. The charge transfer switch is configured to transfer the charge from the light-receiving element to the floating diffusion a plurality of times for each of the pixel groups in the single image data acquisition period.

Abstract: A semiconductor integrated circuit includes multiple signal processing circuits including a constant current source, a first bias source that generates first bias voltage, a second bias source that generates second bias voltage, a first bias circuit that supplies a first reference current to the first bias source, a second bias circuit that supplies a second reference current to the second bias source, a bias wiring that supplies the first bias voltage and the second bias voltage to a plurality of gates of a transistor that constructs the constant current source, a power source wiring that supplies a power source voltage to each of the first bias source, the second bias source, and the constant current source, a first voltage supplying source that applies a first power source voltage to the power source wiring, and a second voltage supplying that applies a second power source voltage to the power source wiring.

Abstract: A photoelectric conversion device includes a pixel block including a plurality of pixels, a signal generating block, and a signal processing block. Each of the plurality of pixels includes a photoelectric conversion element to photoelectrically convert light striking the photoelectric conversion element into pixel data and output the pixel data; and a reset unit to reset electrical charge of the photoelectrically converted pixel data light and output a reset signal. The signal generating block includes a reference signal generator to generate a reference signal. The signal processing block performs correlated double sampling (CDS) on the reference signal to obtain correction data, and perform CDS on the pixel data and the reset signal to generate an output signal to correct the output signal with the correction data.

Abstract: A semiconductor integrated circuit including a differential amplifier circuit, a first output circuit, a second output circuit, a selection circuit, and a feedback circuit. The differential amplifier circuit is configured to operate at a first source voltage. The first output circuit is configured to receive an output of the differential amplifier circuit, output a first output, and operate at the first source voltage. The second output circuit is configured to receive an output of the differential amplifier circuit, output a second output, and operate at a second source voltage lower than the first source voltage. The selection circuit is configured to select one of the first output from the first output circuit and the second output from the second output circuit according to an operating phase determined by an external control signal. The feedback circuit is connected between the differential amplifier circuit and the selection circuit.

Abstract: A photoelectric conversion device includes a pixel array including one or more linear array, each including plural linearly-arranged pixels; and plural memory circuits, each including plural memory cells. The plural pixels in the pixel array are connected one-to-one to the plural memory cells of the plural memory circuits. Each of the plural pixels alternately outputs a photoelectric conversion value indicating an electric voltage generated in accordance with a light amount of an incident light entering the pixel, and a reset value indicating a reference charge of the pixel, to the memory cell corresponding to the pixel. Each of the plural memory cells temporarily stores the photoelectric conversion value and the reset value output from the pixel corresponding to the memory cell. Each of the plural memory circuits outputs the photoelectric conversion values and the reset values stored in the plural memory cells of the memory circuit, in a predetermined order.

Abstract: An image capturing device includes a photoelectric converter including one of a plurality of pixels, an amplifier, and control circuitry. Each pixel includes at least a photoelectric conversion element, and is configured to output an electrical signal corresponding to an intensity of light received by the photoelectric conversion element. The control circuitry is configured to sequentially drive the plurality of pixels in a time staggered manner such that, during a time from when a certain pixel outputs a reset signal of the certain pixel to the amplifier to when the pixel outputs a signal of the certain pixel to the amplifier, a subsequent pixel of the certain pixel outputs one of a reset signal and a signal of the subsequent pixel to the amplifier. The reset signal represents an electrical signal of a reset voltage to reset a corresponding pixel. The signal represents the electrical signal.

Abstract: A solid-state imaging device includes a substrate having a rectangular shape; a first region configured to extend on the substrate in a length direction of the substrate, and to include a plurality of electrode pads arranged above the substrate through a multilayer interconnection; and a second region configured to extend in the length direction, and to include an imaging element, an optical filter, and an insulating film. The second region extends on the substrate on which the imaging element is arranged. The optical filter is arranged above the substrate and faces the imaging element through the insulating film. The second region extends in parallel to the first region to be apart from the first region by a given distance. The plurality of electrode pads are arranged to be apart from each other by a given space, equal to or smaller than the given distance, in the length direction.

Abstract: A photoelectric conversion device, having a horizontally long rectangular shape, includes a pixel block including pixels; signal processing blocks, arranged along a transverse direction of the photoelectric conversion device, for processing a pixel signal; a power source voltage supply block for supplying a power source voltage. The pixel includes a photoelectric conversion element for performing a photoelectric conversion, and a charge/voltage conversion unit, including a first amplifier, for converting the converted charge into a voltage. In the pixel block, columns are arranged in a longitudinal direction. Each column is set as a unit of signal processing including a predetermined number of pixels. Vertical power feeding wirings for feeding the power source voltage to the columns of the pixel block, from the transverse direction, are arranged.

Abstract: An analog signal bus driving circuit includes a plurality of signal sources, a plurality of signal output amplifiers, a plurality of shield drive amplifiers, and a time-division control circuit. The plurality of signal sources generate a plurality of analog signals. The plurality of signal output amplifiers output the plurality of analog signals to at least one signal line. The plurality of shield drive amplifiers output the plurality of analog signals to a shield line. The shield line extends along the at least one signal line to at least partially surround the at least one signal line. The time-division control circuit sequentially drives the plurality of signal output amplifiers in a time-division manner to sequentially output the plurality of analog signals in a time-division manner from the plurality of signal sources to the at least one signal line.

Abstract: A semiconductor integrated circuit includes multiple signal processing circuits including a constant current source, a first bias source that generates first bias voltage, a second bias source that generates second bias voltage, a first bias circuit that supplies a first reference current to the first bias source, a second bias circuit that supplies a second reference current to the second bias source, a bias wiring that supplies the first bias voltage and the second bias voltage to a plurality of gates of a transistor that constructs the constant current source, a power source wiring that supplies a power source voltage to each of the first bias source, the second bias source, and the constant current source, a first voltage supplying source that applies a first power source voltage to the power source wiring, and a second voltage supplying that applies a second power source voltage to the power source wiring.

Abstract: A semiconductor integrated circuit includes multiple signal processing circuits including a constant current source, a first bias source that generates first bias voltage, a second bias source that generates second bias voltage, a first bias circuit that supplies a first reference current to the first bias source, a second bias circuit that supplies a second reference current to the second bias source, a bias wiring that supplies the first bias voltage and the second bias voltage to a plurality of gates of a transistor that constructs the constant current source, a power source wiring that supplies a power source voltage to each of the first bias source, the second bias source, and the constant current source, a first voltage supplying source that applies a first power source voltage to the power source wiring, and a second voltage supplying that applies a second power source voltage to the power source wiring.

Abstract: A solid-state imaging device includes a pixel circuit including a plurality of photoelectric conversion elements and configured to output a signal level and a reset level, an analog correlated double sampling (CDS) circuit connected to the pixel circuit and configured to perform correlated double sampling in an analog region based on the signal level and the reset level and output a result of the correlated double sampling, an analog-digital (AD) conversion circuit connected to the analog CDS circuit and configured to convert two different analog signals output from the analog CDS circuit into two digital signals, a signal processing circuit connected to the AD conversion circuit and configured to obtain a difference between the two different digital signals output from the AD conversion circuit; and a reference voltage generating circuit to output a first reference voltage that defines a clamp level of the analog CDS circuit.

Abstract: A photoelectric conversion element comprises: a plurality of photodetectors that perform photoelectric conversion per pixel to output an analog image signal, and that are arranged on a straight line; and wirings that are formed on a wiring layer, and that are enabled to be used as at least one of a signal line used in a peripheral circuit of the photodetector, a power source, and a ground, wherein the photodetector is formed to have a first shaded region and a second shaded region in which light is shaded by the wirings that are positioned on the straight line sandwiching an opening, respectively, when light that has passed through the opening that opens being sandwiched by the wirings positioned on the straight line is incident perpendicularly on a light receiving surface of the photodetector.

Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.

Abstract: A solid-state imaging device includes: a valid area including pixels that are not shielded from light; a first light-blocked area and a second light-blocked area each including pixels that are shielded from light; an analog-to-digital converting unit to convert the electric charge accumulated by the pixels belonging to the first light-blocked area, the valid area, and the second light-blocked area, to image data at a time; a signal reading unit to read light-blocked data obtained from the first light-blocked area and the second light-blocked area, and valid data obtained from the valid area, in units of pixels; a reference black level estimating unit to estimate a reference black level of the light-blocked data; and a level correction unit to correct, based on the estimated reference black level, a size of the valid data obtained simultaneously with the light-blocked data used in estimating the reference black level.

Abstract: A solid-state image sensor includes a pixel unit having a plurality of pixels arranged in matrix, a read signal processing circuit, a test signal output circuit, a test signal generating circuit, and a control circuit that controls operations of the above mentioned circuits. Each of the plurality of pixels outputs a pixel signal that is obtained by amplifying a photoelectrically converted signal using an output amplifier in one or more pixel units. The read signal processing circuit reads the pixel signal output from the pixel unit in units of one or more pixels to a corresponding signal line and processes the pixel signal. The test signal output circuit, having a test output amplifier for each signal line, outputs a signal from the test output amplifier to the signal line in response to a test signal input to the test output amplifier. The test signal generating circuit generates the test signal.

Abstract: A semiconductor integrated circuit includes multiple signal processing circuits including a constant current source, a first bias source that generates first bias voltage, a second bias source that generates second bias voltage, a first bias circuit that supplies a first reference current to the first bias source, a second bias circuit that supplies a second reference current to the second bias source, a bias wiring that supplies the first bias voltage and the second bias voltage to a plurality of gates of a transistor that constructs the constant current source, a power source wiring that supplies a power source voltage to each of the first bias source, the second bias source, and the constant current source, a first voltage supplying source that applies a first power source voltage to the power source wiring, and a second voltage supplying that applies a second power source voltage to the power source wiring.

Abstract: A solid-state imaging device includes a substrate having a rectangular shape; a first region configured to extend on the substrate in a length direction of the substrate, and to include a plurality of electrode pads arranged above the substrate through a multilayer interconnection; and a second region configured to extend in the length direction, and to include an imaging element, an optical filter, and an insulating film. The second region extends on the substrate on which the imaging element is arranged. The optical filter is arranged above the substrate and faces the imaging element through the insulating film. The second region extends in parallel to the first region to be apart from the first region by a given distance. The plurality of electrode pads are arranged to be apart from each other by a given space, equal to or smaller than the given distance, in the length direction.

Abstract: A photoelectric conversion element includes a light receiving element, a buffer unit, a current control circuit, and an elimination circuit. The light receiving element generates electrical charge according to an amount of light received. The buffer unit buffers and outputs a voltage signal according to the electrical charge generated by the light receiving element. When the buffer unit outputs the voltage signal, the current control circuit controls electric current flowing through the buffer unit so as to be a predetermined amount of electric current. The elimination circuit eliminates high-frequency components in a band equal to or higher than a predetermined band from the voltage signal output from the buffer unit.