Abstract: A spread spectrum clock generator includes a phase comparator to detect a phase difference between a reference input clock signal and a feedback signal and output a control voltage, a voltage controlled oscillator to generate an output clock signal with a frequency in line with the control voltage, a phase selector to select any of equally divided phases of one cycle of the output clock signal, generate and transmit a phase shift clock signal to the phase comparator as the feedback signal, and a phase controller to decide a phase of the rising edge of the phase shift clock signal and control the phase selector to select the decided phase, and generate a second phase shift amount, decide the rising edge of the phase shift clock signal to and subject the output clock signal to spread spectrum modulation by the second phase shift amount.

Abstract: An image reading signal processing IC includes three circuits which independently process input analog image signals of three primary colors. Each circuit includes an ADC which converts amplified analog image signals into digital image data. Each circuit also includes an LVDS processing circuit which outputs the digital image data in a low voltage differential signaling level. Each circuit further includes a test pattern generating circuit connected between the ADC and the LVDS processing circuit for generating digital data of a test pattern. The image reading signal processing IC additionally includes an operational mode determination information input unit which inputs operational mode determination information to the test pattern generating circuit. Further, the image reading signal processing IC includes a switching unit which switches one of the digital data of the test patterns to any one or more of main scanning direction gradation pattern data and sub scanning direction gradation pattern data.

Abstract: When a light source is in off state, a gray level of image data on a pixel-by-pixel basis is generated as a first black level and an average of gray levels of a portion of the image data corresponding to optical black image portions of sensor chips is generated as a second black level. After that, when an image of an original is read, an average of gray levels of the black image data on a line-by-line basis is generated as a third black level. The first black level is subtracted from a gray level of the image data on a line-by-line basis (an offset correction), and a difference between the third black level and the second black level is added to a gray level of the image data after being subjected to the subtraction on a line-by-line basis.

Abstract: A clock-signal generating unit generates temporally-continuous clock signals. A spread-spectrum clock-signal generating unit generates a spread-spectrum clock signal by modulating a frequency spectrum of a clock signal generated by the clock-signal generating unit. A signal delaying unit generates a fixed delay unaffected by a spread spectrum from the spread-spectrum clock signal generated by the spread-spectrum clock-signal generating unit, and delays a phase of the spread-spectrum clock signal based on an amount of the fixed delay.

Abstract: A spread spectrum clock generator includes a phase comparator to detect a phase difference between a reference input clock signal and a feedback signal and output a control voltage, a voltage controlled oscillator to generate an output clock signal with a frequency in line with the control voltage, a phase selector to select any of equally divided phases of one cycle of the output clock signal, generate and transmit a phase shift clock signal to the phase comparator as the feedback signal, and a phase controller to decide a phase of the rising edge of the phase shift clock signal and control the phase selector to select the decided phase, and generate a second phase shift amount, decide the rising edge of the phase shift clock signal to and subject the output clock signal to spread spectrum modulation by the second phase shift amount.

Abstract: In an image reading device, a sampling-and-holding circuit generates a plurality of analog image signals by sampling an image signal at each sampling-and-holding timing and holding sampled image signals for a predetermined amount of time, an analog-to-digital converting unit converts the analog image signals into a plurality of digital image signals at each sampling-and-holding timing, a phase regulating unit performs phase regulation of each sampling-and-holding timing based on corresponding digital image signals to obtain phase-regulated sampling-and-holding timing. The sampling-and-holding circuit generates the analog image signal at each phase-regulated sampling-and-holding timing.

Abstract: A clock output from a quartz oscillator is input to a timing generator via a spread spectrum clock generator that spreads the spectrum of the clock. The clock is multiplexed by a phase locked loop to generate pixel clocks having the same frequency as a pixel frequency. The pixel clock is input to a delay locked loop, which generates a multi-layer clock by dividing each cycle of the pixel clock by 60. Clock generating units select a required phase from the multi-layer clock, thereby generating a timing signal. The phase, the pulse width, and the output period of the timing signal are controlled as desired by setting appropriate values to a register.

Abstract: A read signal processor includes an output unit that serializes a plurality of bits of digital data for each of the colors to obtain a plurality of serial signals, converts the serial signals to a plurality of low-amplitude differential signals, and outputs the serial low-amplitude differential signals.

Abstract: An image reading apparatus and an image forming apparatus including the image reading apparatus. The image reading apparatus includes a photoelectric converter to convert incident light into an analog image signal, a drive unit to drive the photoelectric converter by a frequency modulated clock signal, an overlapping circuit to overlap an anti-phase analog signal to the analog image signal fluctuating according to the frequency modulated clock signal with a same amount of fluctuation as that of the analog image signal, and an analog digital converter to convert the overlapped analog image signal into a digital output.

Abstract: Example embodiments of the present invention relate generally to a buffer circuit capable of suppressing the adverse influence of excessive voltage or current output from a photoelectric converting element on an analog signal processing circuit coupled to the photoelectric converting element, and an image reading apparatus or image forming apparatus incorporating the photoelectric converting element, the buffer circuit, and the analog signal processing circuit.

Abstract: A reference-signal generating unit generates a reference signal for generating a driving signal to drive each unit of the image reading device. A frequency modulating unit modulates frequency of the reference signal, thereby generating a frequency-modulated reference signal. A driving-signal generating unit generates the driving signal from the frequency-modulated reference signal. A photoelectric converting unit converts an incident light into an analog image signal using the driving signal. An AD converting unit converts the analog image signal into a digital image signal. A correcting unit corrects the digital image signal by generating a correction signal for eliminating a noise superimposed on the digital image signal using the frequency-modulated reference signal and adding the correction signal to the digital image signal.

Abstract: An image signal processing circuit including a gain control circuit capable of performing gain control operation, and an image reading device or an image forming apparatus incorporating the image signal processing circuit.

Abstract: When a light source is in off state, a gray level of image data on a pixel-by-pixel basis is generated as a first black level and an average of gray levels of a portion of the image data corresponding to optical black image portions of sensor chips is generated as a second black level. After that, when an image of an original is read, an average of gray levels of the black image data on a line-by-line basis is generated as a third black level. The first black level is subtracted from a gray level of the image data on a line-by-line basis (an offset correction), and a difference between the third black level and the second black level is added to a gray level of the image data after being subjected to the subtraction on a line-by-line basis.

Abstract: A clock output from a quartz oscillator is input to a timing generator via a spread spectrum clock generator that spreads the spectrum of the clock. The clock is multiplexed by a phase locked loop to generate pixel clocks having the same frequency as a pixel frequency. The pixel clock is input to a delay locked loop, which generates a multi-layer clock by dividing each cycle of the pixel clock by 60. Clock generating units select a required phase from the multi-layer clock, thereby generating a timing signal. The phase, the pulse width, and the output period of the timing signal are controlled as desired by setting appropriate values to a register.

Abstract: A clock-signal generating unit generates temporally-continuous clock signals. A spread-spectrum clock-signal generating unit generates a spread-spectrum clock signal by modulating a frequency spectrum of a clock signal generated by the clock-signal generating unit. A signal delaying unit generates a fixed delay unaffected by a spread spectrum from the spread-spectrum clock signal generated by the spread-spectrum clock-signal generating unit, and delays a phase of the spread-spectrum clock signal based on an amount of the fixed delay.

Abstract: In an image reading device, a sampling-and-holding circuit generates a plurality of analog image signals by sampling an image signal at each sampling-and-holding timing and holding sampled image signals for a predetermined amount of time, an analog-to-digital converting unit converts the analog image signals into a plurality of digital image signals at each sampling-and-holding timing, a phase regulating unit performs phase regulation of each sampling-and-holding timing based on corresponding digital image signals to obtain phase-regulated sampling-and-holding timing. The sampling-and-holding circuit generates the analog image signal at each phase-regulated sampling-and-holding timing.

Abstract: A first clamping unit clamps a base voltage of an input image signal to a predetermined reference voltage. A sampling-and-holding unit samples and holds the image signal after clamping or a reference signal that becomes the base voltage of the image signal. An amplifying unit amplifies the image signal sampled and held by the sampling-and-holding unit. An analog-to-digital converting unit converts the image signal after amplification into a digital image signal. A second clamping unit clamps the reference signal to a predetermined voltage.

Abstract: An image signal processing circuit including a gain control circuit capable of performing gain control operation, and an image reading device or an image forming apparatus incorporating the image signal processing circuit.

Abstract: A document reading apparatus arranged to reduce inconsistencies in the output signals of its linear image sensor is provided. The document reading apparatus includes a linear image sensor, a light source control circuit, and a light source driver. The light source control circuit has a pulse generator that generates control pulses having a prescribed frequency and a pulse period that is shorter than an accumulation period of the linear image sensor, the accumulation period being indicated by a timing signal that represents the accumulation period and a non-accumulation period. The light source control circuit also has a synchronization output unit that outputs a prescribed number of trigger pulses in synchronization with the timing signal and the control pulses. The light source driver drives the light source in response to the trigger pulses.

Abstract: An image reading apparatus and an image forming apparatus including the image reading apparatus. The image reading apparatus includes a photoelectric converter to convert incident light into an analog image signal, a drive unit to drive the photoelectric converter by a frequency modulated clock signal, an overlapping circuit to overlap an anti-phase analog signal to the analog image signal fluctuating according to the frequency modulated clock signal with a same amount of fluctuation as that of the analog image signal, and an analog digital converter to convert the overlapped analog image signal into a digital output.