Abstract: A read signal processor includes an output unit that serializes a plurality of bits of digital data for each of the colors to obtain a plurality of serial signals, converts the serial signals to a plurality of low-amplitude differential signals, and outputs the serial low-amplitude differential signals.

Abstract: A signal processing IC that receives analog signals each corresponding to one of three colors from a color linear image sensor includes two systems of input-signal processing for each color each including at least a sample-and-hold circuit, a multiplexer circuit, a variable gain amplifier, and an A/D converter circuit. The sample-and-hold circuit samples and holds an analog signal. The multiplexer circuit multiplexes analog signals of the two systems subjected to sampling and holding into a signal of one system. The variable gain amplifier amplifies the signal output from the multiplexer circuit. The A/D converter circuit converts the amplified signal to digital data.

Abstract: An image reading signal processing IC is disclosed which includes three circuits to which corresponding analog image signals of three primary colors of a document read by a CCD are input. In each of the three circuits, a test pattern generating circuit is disposed between an ADC and an LVDS processing circuit. Further, the image reading signal processing IC includes an operational mode determination information input unit formed of a TG & I/F and an OR gate. An operational mode of the test pattern generating circuit is switched between a normal mode for outputting digital image data output from the ADC and a test pattern output mode for outputting digital data of a test pattern generated by the test pattern generating circuit based on operational mode determination information input from the operational mode determination information input unit.

Abstract: Example embodiments of the present invention relate generally to a buffer circuit capable of suppressing the adverse influence of excessive voltage or current output from a photoelectric converting element on an analog signal processing circuit coupled to the photoelectric converting element, and an image reading apparatus or image forming apparatus incorporating the photoelectric converting element, the buffer circuit, and the analog signal processing circuit.

Abstract: An image processing apparatus including a scanner with a direct control section configured to control a scanning operation of the scanner so as to input image information from an original document and a main body configured to process the image information. The main body includes a control section configured to perform an initializing process for the main body. Further, a homing operation of the scanner is performed by the direct control section independently of the initializing process of the control section of the main body, when power is supplied to the image processing apparatus or when the image processing apparatus is returned from a shutdown state.

Abstract: A document reading apparatus arranged to reduce inconsistencies in the output signals of its linear image sensor is provided. The document reading apparatus includes a linear image sensor, a light source control circuit, and a light source driver. The light source control circuit has a pulse generator that generates control pulses having a prescribed frequency and a pulse period that is shorter than an accumulation period of the linear image sensor, the accumulation period being indicated by a timing signal that represents the accumulation period and a non-accumulation period. The light source control circuit also has a synchronization output unit that outputs a prescribed number of trigger pulses in synchronization with the timing signal and the control pulses. The light source driver drives the light source in response to the trigger pulses.

Abstract: A digital-to-analog converter including a signal generator, a low-weighted value manager, and a voltage smoothing circuit. The signal generator performs a pulse width modulation (pwm) based on a reference clock signal and upper nh bits of the n-bit digital data to generate a first pulse-width-modulated signal having first pulses having a first pulse width in response to a value of the upper nh bits of the n-bit digital data and a pwm cycle signal. The low-weighted value manager divides a pulse width in response to a value of the lower nl bits of the n-bit digital data into fraction pulse widths, respectively adds the fraction pulse widths to the first pulses, and generates a second pulse-width-modulated signal having second pulses including the first pulse width and one of the fraction pulse widths.

Abstract: An image processing apparatus, method, and computer program product including a carriage for carrying an image reading device; a white plate arranged above a track of the carriage, and read by the image reading device for adjusting a reading level; a home position sensor to detect the position of the carriage; and a controller to control the movement of the carriage. The controller is configured to determine the direction of movement of the carriage based on the output of the home position sensor, and to perform a tentative homing operating when the home position sensor changes its output after the carriage is moved.

Abstract: A digital-to-analog converter including a signal generator, a low-weighted value manager, and a voltage smoothing circuit. The signal generator performs a pulse width modulation (pwm) based on a reference clock signal and upper nh bits of the n-bit digital data to generate a first pulse-width-modulated signal having first pulses having a first pulse width in response to a value of the upper nh bits of the n-bit digital data and a pwm cycle signal. The low-weighted value manager divides a pulse width in response to a value of the lower nl bits of the n-bit digital data into fraction pulse widths, respectively adds the fraction pulse widths to the first pulses, and generates a second pulse-width-modulated signal having second pulses including the first pulse width and one of the fraction pulse widths.

Abstract: An image processing apparatus, method and computer program product, wherein an initializing process of a scanner is performed in a short period of time when a return operation from a shutdown state is performed. A carriage of the scanner stays in a white level range when the main body is put in the shutdown state. Thus, the scanner immediately makes an automatic adjustment to its image reading level when the return operation from the shutdown state is started. The carriage detects an original position for a scanning operation while it moves to a standby position after the automatic adjustment is made. Thereby, the initializing process of the scanner is performed eliminating an operation of the carriage in which the carriage moves to the white plate range to read the white plate.

Abstract: An image processing apparatus including a scanner with a direct control section configured to control a scanning operation of the scanner so as to input image information from an original document and a main body configured to process the image information. The main body includes a control section configured to perform an initializing process for the main body. Further, a homing operation of the scanner is performed by the direct control section independently of the initializing process of the control section of the main body, when power is supplied to the image processing apparatus or when the image processing apparatus is returned from a shutdown state.

Abstract: A variable gain amplifier has a large variable range of a gain with respect to an analog signal having a level changing at a high-speed. The variable gain amplifier is provided with a digital-setting-type signal attenuator having a resistor string including a plurality of resistors connected in series. A maximum attenuation-factor limiting resistor is connected between the resistor string and a ground. Each of the analog switches is connected to respective points of the resistor string. A decoder generates a control signal for selecting at least one of the analog switches, the control signal being generated based on setting data provided from an external device. A voltage across the resistor string is divided by the resistors included in the resistor string, and the divided voltage is output to an amplifier from at least one of the analog switches selected by the control signal generated by the decoder.

Abstract: A photoelectric transfer device includes at least one photoelectric transfer cell having the following elements: A photoelectric transfer element generates a photoelectric current based on a quantity of incident light. An amplifier element includes first FET and functions as a source follower in which a source voltage of the first FET is varied so as to follow up a gate voltage thereof. A read unit outputs, as an output signal, the source voltage of the source follower. The photoelectric transfer element is connected to a gate and source of the amplifier element so that a voltage between the gate and source of the amplifier element is applied across the photoelectric transfer element.