Abstract: An imaging device includes a plurality of arranged imaging elements each including: a light-receiving element configured to generate charge from received light by photoelectric conversion, a floating diffusion configured to convert the charge generated by the light-receiving element into voltage, a charge transfer switch configured to transfer the charge from the light-receiving element to the floating diffusion, a reset switch configured to reset the voltage of the floating diffusion, and a source follower configured to amplify the voltage of the floating diffusion. The reset switch is configured to reset the voltage of the floating diffusion a plurality of times for each of predetermined pixel groups in a single image data acquisition period. The charge transfer switch is configured to transfer the charge from the light-receiving element to the floating diffusion a plurality of times for each of the pixel groups in the single image data acquisition period.

Abstract: An imaging device includes a pixel region in which a plurality of pixels and a plurality of charge-to-voltage conversion circuits are arranged in matrix. The pixels include photoelectric conversion elements that output charges in accordance with intensity of received light. The charge-to-voltage conversion circuits convert the charges output from the pixels into voltage signals. The pixel region includes an isolated region including isolated shaded pixels covered with a first shading metal of the same layer as a layer of wiring metals of the charge-to-voltage conversion circuits, and an isolated pixel that is not covered with the metal. All the pixels surrounding the isolated pixel in the isolated region are the isolated shaded pixels.

Abstract: A solid-state imaging device includes a pixel circuit including a plurality of photoelectric conversion elements and configured to output a signal level and a reset level, an analog correlated double sampling (CDS) circuit connected to the pixel circuit and configured to perform correlated double sampling in an analog region based on the signal level and the reset level and output a result of the correlated double sampling, an analog-digital (AD) conversion circuit connected to the analog CDS circuit and configured to convert two different analog signals output from the analog CDS circuit into two digital signals, a signal processing circuit connected to the AD conversion circuit and configured to obtain a difference between the two different digital signals output from the AD conversion circuit; and a reference voltage generating circuit to output a first reference voltage that defines a clamp level of the analog CDS circuit.

Abstract: A solid-state imaging device includes a photoelectric converter including a plurality of light receiving elements arranged along one direction in correspondence with each color of received light, each light receiving element generating an electric charge corresponding to an amount of received light, an electric charge storage unit including a plurality of capacitors storing the electric charges generated by the respective light receiving elements, and a signal processing unit configured to process each of the electric charges stored by the plurality of capacitors as a signal. The electric charge storage unit is disposed so as to oppose the signal processing unit across the photoelectric converter.

Abstract: A photoelectric conversion element comprises: a plurality of photodetectors that perform photoelectric conversion per pixel to output an analog image signal, and that are arranged on a straight line; and wirings that are formed on a wiring layer, and that are enabled to be used as at least one of a signal line used in a peripheral circuit of the photodetector, a power source, and a ground, wherein the photodetector is formed to have a first shaded region and a second shaded region in which light is shaded by the wirings that are positioned on the straight line sandwiching an opening, respectively, when light that has passed through the opening that opens being sandwiched by the wirings positioned on the straight line is incident perpendicularly on a light receiving surface of the photodetector.

Abstract: A photoelectric conversion element comprises: a plurality of photodetectors that perform photoelectric conversion per pixel to output an analog image signal, and that are arranged on a straight line; and wirings that are formed on a wiring layer, and that are enabled to be used as at least one of a signal line used in a peripheral circuit of the photodetector, a power source, and a ground, wherein the photodetector is formed to have a first shaded region and a second shaded region in which light is shaded by the wirings that are positioned on the straight line sandwiching an opening, respectively, when light that has passed through the opening that opens being sandwiched by the wirings positioned on the straight line is incident perpendicularly on a light receiving surface of the photodetector.

Abstract: An LVDS driver includes a plurality of differential signal generators to receive adjustment signals generated by a slew rate adjusting unit and generate a differential signal for transmission to a plurality of LVDS receivers through a transmission line. The slew rate adjusting unit receives slew rate control signals from a slew rate control signal setting unit, and a slew rate of the differential signal is adjusted based on the adjustment signals.

Abstract: A photoelectric conversion element includes a light receiving element, a buffer unit, a current control circuit, and an elimination circuit. The light receiving element generates electrical charge according to an amount of light received. The buffer unit buffers and outputs a voltage signal according to the electrical charge generated by the light receiving element. When the buffer unit outputs the voltage signal, the current control circuit controls electric current flowing through the buffer unit so as to be a predetermined amount of electric current. The elimination circuit eliminates high-frequency components in a band equal to or higher than a predetermined band from the voltage signal output from the buffer unit.

Abstract: A photoelectric conversion element comprises: a plurality of photodetectors that perform photoelectric conversion per pixel to output an analog image signal, and that are arranged on a straight line; and wirings that are formed on a wiring layer, and that are enabled to be used as at least one of a signal line used in a peripheral circuit of the photodetector, a power source, and a ground, wherein the photodetector is formed to have a first shaded region and a second shaded region in which light is shaded by the wirings that are positioned on the straight line sandwiching an opening, respectively, when light that has passed through the opening that opens being sandwiched by the wirings positioned on the straight line is incident perpendicularly on a light receiving surface of the photodetector.

Abstract: A signal processing circuit 4 includes a clock circuit 24 which generates a clock signal which has been subjected to spread spectrum modulation and supplies the clock signal to a photoelectric conversion element; a AD converter 15 which performs AD conversion on an image signal obtained by the photoelectric conversion element; a noise detecting circuit 21 which detects a noise amplitude of a noise signal that is caused by the spread spectrum modulation of the clock signal and is included in the image signal which has been AD converted; and an analog correction circuit 23 and an digital correction circuit 22 that calculate a correction factor based on the noise amplitude, generate a correction signal by multiplying the digital modulation signal by the correction factor, and superimpose the correction signal onto the image signal at an input side or an output side of the AD converter.

Abstract: An LVDS driver is provided that includes a plurality of differential signal generators configured to generate a differential signal to transmit the generated differential signal to a plurality of LVDS receivers through a transmission line. A slew rate of the differential signal is controlled for each output of the differential signal.

Abstract: An image processing apparatus includes an amplifying unit for, during a main scanning line period, amplifying an analog image signal input from a photoelectric conversion element and outputting the signal; an A/D converting unit for analog/digital-converting the signal to digital image data and outputting the data; and a digital offset correcting unit for performing a low-pass filter calculation based on the data to obtain an average value, calculating, based on the average value, a digital correction value used for correcting the data to obtain a desired black offset level, and performing correction on the data using the value. The digital offset correcting unit compares the value to a threshold, reduces the value to be equal to or less than the threshold if the value is equal to or greater than the threshold and updates the value to the reduced value, and performs the low-pass filter calculation and calculates the value.

Abstract: A sampling clock generator circuit includes a reference clock generator, a sampling hold circuit, a sampling clock generator to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit, a phase determining element to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator, and a controller to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero.

Abstract: A fractional PLL circuit includes: a phase comparator for detecting a phase difference, and which outputs a controlled voltage; a voltage-controlled oscillator for generating and outputting an output clock signal; a phase-selection circuit for selecting any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generating a phase-shift clock signal having a rising edge in the selected phase, and outputting the phase-shift clock signal to the phase comparator; and a phase controller for determining a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controlling the phase-selection circuit so as to select the determined phase.

Abstract: A fractional PLL circuit includes: a phase comparator for detecting a phase difference, and which outputs a controlled voltage; a voltage-controlled oscillator for generating and outputting an output clock signal; a phase-selection circuit for selecting any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generating a phase-shift clock signal having a rising edge in the selected phase, and outputting the phase-shift clock signal to the phase comparator; and a phase controller for determining a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controlling the phase-selection circuit so as to select the determined phase.

Abstract: A sampling clock generator circuit includes a reference clock generator, a sampling hold circuit, a sampling clock generator to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit, a phase determining element to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator, and a controller to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero.

Abstract: A first clamping unit clamps a base voltage of an input image signal to a predetermined reference voltage. A sampling-and-holding unit samples and holds the image signal after clamping or a reference signal that becomes the base voltage of the image signal. An amplifying unit amplifies the image signal sampled and held by the sampling-and-holding unit. An analog-to-digital converting unit converts the image signal after amplification into a digital image signal. A second clamping unit clamps the reference signal to a predetermined voltage.

Abstract: An image processing apparatus includes an amplifying unit for, during a main scanning line period, amplifying an analog image signal input from a photoelectric conversion element and outputting the signal; an A/D converting unit for analog/digital-converting the signal to digital image data and outputting the data; and a digital offset correcting unit for performing a low-pass filter calculation based on the data to obtain an average value, calculating, based on the average value, a digital correction value used for correcting the data to obtain a desired black offset level, and performing correction on the data using the value. The digital offset correcting unit compares the value to a threshold, reduces the value to be equal to or less than the threshold if the value is equal to or greater than the threshold and updates the value to the reduced value, and performs the low-pass filter calculation and calculates the value.

Abstract: A signal processing circuit 4 includes a clock circuit 24 which generates a clock signal which has been subjected to spread spectrum modulation and supplies the clock signal to a photoelectric conversion element; a AD converter 15 which performs AD conversion on an image signal obtained by the photoelectric conversion element; a noise detecting circuit 21 which detects a noise amplitude of a noise signal that is caused by the spread spectrum modulation of the clock signal and is included in the image signal which has been AD converted; and an analog correction circuit 23 and an digital correction circuit 22 that calculate a correction factor based on the noise amplitude, generate a correction signal by multiplying the digital modulation signal by the correction factor, and superimpose the correction signal onto the image signal at an input side or an output side of the AD converter.

Abstract: A reference-signal generating unit generates a reference signal for generating a driving signal to drive other units of the image reading device. A frequency modulating unit modulates frequency of the reference signal, thereby generating a frequency-modulated reference signal. A driving-signal generating unit generates the driving signal from the frequency-modulated reference signal. A photoelectric converting unit converts an incident light into an analog image signal using the driving signal. An AD converting unit converts the analog image signal into a digital image signal. A correcting unit corrects the digital image signal by generating a correction signal for eliminating a noise superimposed on the digital image signal using the frequency-modulated reference signal and adding the correction signal to the digital image signal.