Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.

Abstract: A two-dimensional filter arithmetic device comprises a picture memory (300), a line memory (400), a vertical filtering unit (100) which includes nine first filter modules installed in parallel, a buffer (500) for timing adjustments, and a horizontal filtering unit (200) which includes four second filter modules installed in parallel. From the line memory (400), the pixel values of nine full pels per line are inputted in parallel to the vertical filtering unit (100), nine vertically-filtered values of half pels are generated and inputted to the horizontal filtering unit (200); thereby, four two-dimensionally-filtered values of half pels are generated.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

Abstract: The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

Abstract: To provide an information processing apparatus capable of performing switching between an exception handler and normal processing, the information processing apparatus comprising: An information processing apparatus comprising: a processor; a data processing unit operable to perform particular processing upon receiving a processing request from the processor; an interrupt controller operable to issue an interrupt request to the processor; and an exception control unit operable to control the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line, the data processing unit includes a notification unit operable to notify, via the dedicated line, the exception control unit of status information showing a current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execut

Abstract: In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.

Abstract: The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread.

Abstract: A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit sequentially decodes an instruction, and performs a control based on the instruction. When decoding a coprocessor operation instruction to request the coprocessor to perform an operation, which includes operands designating a type of an operation to be performed by the coprocessor, a first register storing data to be used for the operation, and a second register to store data obtained by the operation, the control unit requests the coprocessor to perform the designated type of operation by using a content in the first register, and causes the second register to store a result of the operation.