Abstract: A non-volatile memory device is disclosed that can reduce the time required for the initialization process. A non-volatile memory device includes a non-volatile memory array having a plurality of pages. Each page includes a plurality of non-volatile memory cells, a first region for storing data, and a second region for storing control data that is associated with the data of the first region. The non-volatile memory device further includes a read out unit for reading out data from the pages, and a data buffer for temporarily storing data that has been read out from the pages by the read out unit. When reading out the control data, the read out unit reads out the second regions, across a plurality of pages, at one time.

Abstract: In a resource request arbitration apparatus according to the present invention, a request masking unit masks a memory access request REQ that is issued by a resource requesting device at over a minimum frequency needed for the resource requesting device, and an arbitrating unit acknowledges one of the memory access requests RREQ that are not suspended by the request masking unit, based on a predetermined static order of priority. With this resource request arbitration apparatus, the arbitrating unit do not have to concern anything other than the predetermined priority order among the memory access requesting units, and an easy and plain arbitration system based on the static priority order ensures the minimum frequency for acknowledging the resource requests that each memory access requesting unit needs.

Abstract: The speed of decoding processing for variable-length coded image data is improved.

Abstract: A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit sequentially decodes an instruction, and performs a control based on the instruction. When decoding a coprocessor operation instruction to request the coprocessor to perform an operation, which includes operands designating a type of an operation to be performed by the coprocessor, a first register storing data to be used for the operation, and a second register to store data obtained by the operation, the control unit requests the coprocessor to perform the designated type of operation by using a content in the first register, and causes the second register to store a result of the operation.

Abstract: A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.

Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

Abstract: The invention provides a circuit used in a padding and other processes necessary for coding of objects, and performs at high speed pixel processing to generate pixel values to be assigned to cells, using pixel values in a reference area, which includes cells with and without a pixel value. A cell address outputting unit (i) obtains cell addresses indicating positions of a predetermined number of cells serially arranged and binary signals expressing whether those cells each have a pixel value, and (ii) selects, for each cell, two of the obtained cell addresses corresponding to a part of binary signals each expressing that a cell has a pixel value, and outputs the selected cell addresses. A reading unit reads pixel values of the cells at the outputted cell addresses. An operating unit calculates the average of the two read pixel values and outputs the average as a pixel value.

Abstract: In a system that provides CAD layout-design information, by having the user acquire information such as circuit design or CAD layout data registered in a database, the user can analyze the acquired information, so there is a possibility that circuit-design or circuit-board-design know-how could be leaked. With this invention, a characteristic-parameter-extraction means extracts characteristic parameters from a position where there is a possibility of the occurrence of poor electrical characteristics due to an influence of the CAD layout of the input CAD layout data. A correction-determination means determines whether or not it is necessary to correct the layout by comparing the characteristic parameters and correction-determination standards that correspond to poor electrical characteristics read from a database. This makes it possible to check the electrical characteristics of the CAD layout without making available to the user the correction-determination standards or determination method.

Abstract: A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.

Abstract: A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.

Abstract: In a computer system that concurrently executes a plurality of tasks, a cache controller eliminates the possibility of the hit rate of one task dropping due to execution of another task. A region managing unit manages a plurality of regions in a cache memory in correspondence with a plurality of tasks. An address receiving unit receives, from a microprocessor, an address of a location in a main memory at which data to be accessed to execute one of the plurality of tasks is stored. A caching unit acquires, if the data to be accessed is not stored in the cache memory, a data block including the data from the main memory, and stores the acquired data block into a region in the cache memory corresponding to the task.

Abstract: The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one instruction to all the PEs. When the piece of instruction data includes two instructions, the instruction decoding unit 120 forms all the PEs into two groups, so as to assign one instruction to each group. By making it possible to execute, in parallel, not only one type of instruction but also instructions that are different from each other, it is possible to improve the utilization efficiency of the parallel execution processor 100.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit 41 and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

Abstract: In a resource request arbitration apparatus according to the present invention, a request masking unit masks a memory access request REQ that is issued by a resource requesting device at over a minimum frequency needed for the resource requesting device, and an arbitrating unit acknowledges one of the memory access requests RREQ that are not suspended by the request masking unit, based on a predetermined static order of priority. With this resource request arbitration apparatus, the arbitrating unit do not have to concern anything other than the predetermined priority order among the memory access requesting units, and an easy and plain arbitration system based on the static priority order ensures the minimum frequency for acknowledging the resource requests that each memory access requesting unit needs.

Abstract: A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.

Abstract: A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.