Patents by Inventor Tokuzo Kiyohara

Tokuzo Kiyohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030026487
    Abstract: The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.
    Type: Application
    Filed: August 2, 2002
    Publication date: February 6, 2003
    Inventors: Yoshiyuki Wada, Makoto Hirai, Tokuzo Kiyohara, Kosuke Yoshioka, Hideshi Nishida, Yukiharu Ieda
  • Publication number: 20030007565
    Abstract: A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by means of the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.
    Type: Application
    Filed: December 20, 2001
    Publication date: January 9, 2003
    Inventors: Hiroyuki Morishita, Kosuke Yoshioka, Hideshi Nishida, Makoto Hirai, Ryuji Matsuura, Toshiaki Tsuji, Kozo Kimura, Tokuzo Kiyohara
  • Patent number: 6470376
    Abstract: The counter 52 is set with an initial value of “1” and is a counter with a maximum value of “4”. This counter 52 increments the count value held by the flip-flop 51 in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1,2,3,4. This clock signal is also used by the instruction decode control unit 11 to control the execution of instructions, with the counting by the counter 52 being performed once for each instruction execution performed by the instruction decode control unit 11. The comparator 54 compares the count value counted by the counter 52 with the maximum value “4”, and when the values match, sets the task switching signal chg_task_ex at a “High” value, so that the processing switches to the execution of the next task.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: October 22, 2002
    Assignee: Matsushita Electric Industrial Co., LTD
    Inventors: Takaharu Tanaka, Kiyoshi Maenobu, Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara
  • Patent number: 6462744
    Abstract: When an OSD data storage area for storing OSD data needs to be reserved, an area of a frame storage apparatus that should store macroblocks corresponding to an invisible area on a screen is allocated as the OSD data storage area. There is no degradation in picture quality. When doing so, the data reduction control unit 64 receives an instruction to reserve the OSD data storage area and discards the corresponding macroblocks. The OSD data access unit 63 writes the OSD data into an area of the frame storage apparatus that was assigned to store the discarded macroblocks.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: October 8, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuji Mochida, Tokuzo Kiyohara, Makoto Hirai, Hideshi Nishida
  • Publication number: 20020114528
    Abstract: The speed of decoding processing for variable-length coded image data is improved.
    Type: Application
    Filed: February 1, 2002
    Publication date: August 22, 2002
    Inventors: Takaharu Tanaka, Hideshi Nishida, Sosuke Yoshioka, Tokuzo Kiyohara
  • Publication number: 20020106136
    Abstract: A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.
    Type: Application
    Filed: December 18, 2001
    Publication date: August 8, 2002
    Inventors: Hiroyuki Oka, Hideshi Nishida, Kosuke Yoshioka, Tokuzo Kiyohara, Makoto Hirai, Kozo Kimura, Ryuji Matsuura, Hiroyuki Morishita, Toshiaki Tsuji
  • Patent number: 6414608
    Abstract: A first bit string extracting unit extracts a first bit string. A first bit length judging unit detects a first codeword from the first bit string. A first decoding unit generates a first run-level pair from the first codeword. A second bit string extracting unit extracts a second bit string. A second bit length judging unit detects a second codeword from the second bit string. A second decoding unit generates a second run-level pair from the second codeword. A first inverse quantizing unit inverse quantizes the first level to obtain a DCT coefficient. A second inverse quantizing unit inverse quantizes the second level to obtain a DCT coefficient. A second buffer controller writes the DCT coefficients and their first buffer addresses into a second buffer. A first buffer controller reads the DCT coefficients and the first buffer addresses from the second buffer and writes the DCT coefficients into a first buffer at the respective first buffer addresses.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: July 2, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideshi Nishida, Kosuke Yoshioka, Tokuzo Kiyohara
  • Publication number: 20020041626
    Abstract: A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing.
    Type: Application
    Filed: October 24, 2001
    Publication date: April 11, 2002
    Inventors: Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura
  • Patent number: 6340973
    Abstract: A transfer-target unit outputs commands for data reading and data writing. An address generator generates control signals in accordance with the commands, and outputs the number of bytes of data first transferred by read access. A command generator generates control commands in accordance with the control signals to control an SDRAM. At this time the command generator judges the number of transferred bytes to control so that the SDRAM executes instructions in order from an instruction which is the most efficient in data transfer. That is, in the case where data is read across a bank boundary, the command generator judges which is to be executed first between read processing in a bank 0 and active processing in a bank1, to control the SDRAM. A data processor mediates data transfer between the transfer-target unit and the SDRAM in accordance with the control commands.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: January 22, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Ochiai, Yosuke Furukawa, Yutaka Tanaka, Kozo Kimura, Makoto Hirai, Tokuzo Kiyohara, Hideshi Nishida
  • Patent number: 6310921
    Abstract: A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: October 30, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura
  • Patent number: 6212236
    Abstract: Bitstream analyzing unit 111 fetches a coded block pattern and a coded quantized DCT coefficient from each block in a bitstream. Entropy decoding unit 112 decodes the coded block pattern into a block pattern and decodes the coded quantized DCT coefficient into pairs of a run length and an effectiveness factor. Dequantization unit 115 generates orthogonal transformation coefficients from the pairs of a run length and an effectiveness factor. Inverse Discrete Cosine Transform (IDCT) unit 110 generates a difference image from the orthogonal transformation coefficients. Decode controlling unit 110 instructs first selecting unit 118 to select constants “0”output from first constant generating unit 117 when the image is a “skipped” block. Image storage unit 120 stores a plurality of reference frame pictures having been decoded.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: April 3, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideshi Nishida, Kozo Kimura, Makoto Hirai, Tokuzo Kiyohara
  • Patent number: 6105127
    Abstract: A multithreaded processor for executing multiple instruction streams is provided. This multithreaded processor includes: a plurality of functional units for executing instructions; a plurality of instruction decode units, corresponding to the multiple instruction streams on a one-to-one basis, for respectively decoding an instruction, and producing an instruction issue request for designating to which functional unit the decoded instruction should be issued and requesting for the issuance of the decoded instruction to the designated functional unit; a holding unit for holding the priority level of each instruction stream; and a control unit for deciding which decoded instruction should be issued to a functional unit designated by two or more instruction issue requests at the same time, in accordance with the priority levels held by the holding unit.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: August 15, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kozo Kimura, Tokuzo Kiyohara, Kousuke Yoshioka
  • Patent number: 6075899
    Abstract: An image memory stores a one-screen image by dividing the one-screen image into a plurality of image blocks which are each m pixels wide by n pixels high. The image memory has an array-like storage region storing s*t first chrominance components that compose one image block and s*t second chrominance components that compose the same image block in serial areas between a start area specified by a row address and a first column address and an end area specified by the same row address and a second column address (see FIG. 10). The storage region also stores m*n luminance components that compose the same image block in serial areas between a different start area specified by a different row address and a third column address and an end area are specified by the different row address and a fourth column address.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: June 13, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara, Kozo Kimura
  • Patent number: 5694577
    Abstract: An apparatus is provided, for use in a computer having a register bank and a device for operand fetch and instruction execution, for monitoring a store address to maintain coherency of preloaded data that is fetched by a load operation and should be effected by at least one subsequent store operation. The apparatus includes an address register bank having entries for holding the address of a load having loaded data which should be affected by at least one subsequent store operation. Each of the entries has associated therewith a pre-load flag and a type field, the pre-load flag being set when the load is executed and reset when there is no need to be affected by a subsequent store operation.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 2, 1997
    Assignees: Matsushita Electric Industrial Co., Ltd., The Board of Trustees of the University of Illinois
    Inventors: Tokuzo Kiyohara, Wen-mei W. Hwu, William Chen
  • Patent number: 5535358
    Abstract: In cases where a remarked unit of tag addresses set in effective or access state is not registered in a tag section when a reading request is input, an external access is performed, and the remarked unit of tag addresses and other units of tag addresses respectively set in the access state are prepared in a tag entry preparing unit. In cases where a writing request is input to write a piece of updated word data in a remarked unit of data addresses corresponding to the remarked unit of tag addresses before the external access is finished, the state of the remarked tag entry prepared is changed to the effective state, and the updated word data is written in the remarked unit of data addresses of a data storing unit. Because the remarked unit of tag addresses is set in the effective state, the updated word data written in the remarked unit of data addresses is not replaced with a piece of external word data obtained according to the external access when the external access is finished.
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: July 9, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kozo Kimura, Tokuzo Kiyohara
  • Patent number: 5511172
    Abstract: The present invention discloses a speculative execution processor including a plurality of executing units for processing in parallel a plurality of instructions in an instruction sequence stored in its memory.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: April 23, 1996
    Assignee: Matsushita Electric Co. Ind, Ltd.
    Inventors: Kozo Kimura, Kosuki Yoshioka, Tokuzo Kiyohara
  • Patent number: 5479620
    Abstract: A control device includes a memory storing a plurality of micro instructions. A modifying information generator generates modifying information. A modifying unit receives one of the micro instructions and the modifying information from the memory and the modifying information generator respectively. The modifying unit modifies at least part of the one of the micro instructions with the modifying information.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: December 26, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tokuzo Kiyohara, Kozo Kimura, Takahiro Watanabe
  • Patent number: 5469552
    Abstract: A data processing apparatus having a pipelined architecture, includes an instruction fetch unit for fetching an instruction from a memory; an instruction decode unit for decoding the instruction fetched by the instruction fetch unit, and outputting fetch control data regarding operand fetching and operation control data regarding execution of the instruction; an execution unit for receiving the execution control data directly from the instruction decode unit, and executing a predetermined operation based on the operation control data; and an operand fetch unit for receiving the fetch control data directly from the instruction decode unit, and fetching an operand from a source other than registers in the execution unit. The operand fetch unit fetches the operand concurrently with processing in a second cycle, and subsequent cycles if any, of the operation executed by the execution unit and requiring at least two machine cycles for execution.
    Type: Grant
    Filed: September 22, 1994
    Date of Patent: November 21, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masato Suzuki, Tokuzo Kiyohara
  • Patent number: 5210849
    Abstract: In a cache memory simultaneously conducting updating for a miss and a decision on a miss for the subsequent address, a write flag generated by a control unit is written in a valid flag field. Based on this operation, during an access to an external memory at an occurrence of a miss, a tag field and the valid flag field are simultaneously updated. When updating a data field, a read operation is achieved on the tag and valid flag fields to decide occurrence of miss. Thus, an external memory access for a miss at a next address can be executed at an earlier point of time. Moreover, by the provision of a data latch disposed for an output from the data field, and by reading data at a next address and keeping it in the data latch during a memory read cycle, succeeding hit data can be outputted immediately after a miss processing is completed.
    Type: Grant
    Filed: June 18, 1990
    Date of Patent: May 11, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazunori Takahashi, Tokuzo Kiyohara
  • Patent number: 5197136
    Abstract: A storage holds instructions including a branch instruction and a corresponding branch destination instruction. The instructions are sequentially fetched from the storage to a decoder. The decoder sequentially decodes the fetched instructions and derives commands from the respective instructions. The commands are sequentially transferred from the decoder to an execution unit. The execution unit sequentially executes the transferred commands. The decoder serves to detect the branch instruction. When the branch instruction is detected, a normal instruction fetching process is interrupted and the branch destination instruction is promptly fetched to the decoder. The decoder prevents a command of the branch instruction from being transferred to the execution unit.
    Type: Grant
    Filed: November 19, 1990
    Date of Patent: March 23, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kozo Kimura, Tokuzo Kiyohara, Toshimichi Matsuzaki