Abstract: A central processing unit includes an instruction decoder (1), an operand address computation unit (2), an operand pre-fetch unit (3), a control information buffer (5), an arithmetic unit (4), an instruction fetch unit (6), a chip bus (7), and a bus controller (8). A process relating to the fetch of a memory operand is independent from main pipeline process having an instruction fetching stage, an instruction decoding stage, and an instruction execution stage. As a result, control information (13) in an instruction that the fetch of the memory operand is not required does not pass through the pipeline stage relating to the fetch of the memory operand thereby improving bus band width for memory operand accesses.