Patents by Inventor Tomonori Nakamura
Tomonori Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200408730Abstract: A concentration measurement method for measuring a concentration of impurities includes a step of irradiating a DUT 10 serving as a measurement target object with measurement light and stimulus light subjected to intensity modulation using a modulation signal including a default frequency, a step of outputting a detection signal by detecting an intensity of reflected light from the DUT 10 or transmitted light through the DUT 10, and a step of detecting a phase delay of the detection signal with respect to the modulation signal, obtaining a frequency at which the phase delay has a predetermined value, and estimating a concentration of impurities in the measurement target object on the basis of the frequency.Type: ApplicationFiled: January 17, 2019Publication date: December 31, 2020Applicant: HAMAMATSU PHOTONICS K.K.Inventor: Tomonori NAKAMURA
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Publication number: 20200388521Abstract: A pick-up device 10 for picking up a semiconductor chip 100 attached to a front surface of a sheet material 110 is provided with: a stage 12 that includes a material a part or the entirety of which is capable of transmitting a destaticizing electromagnetic wave having an ionization effect and that attracts and holds a rear surface of the sheet material 110; a jacking-up pin 26 for jacking up the semiconductor chip 100 from the rear side of the stage 12; and a destaticizing mechanism 20 that destaticizes charge generated between the semiconductor chip 100 and the sheet material 110 by irradiating the rear surface of the semiconductor chip 100 with the destaticizing electromagnetic wave that is made to pass through the sheet material 110 from the rear side of the stage 12.Type: ApplicationFiled: January 30, 2018Publication date: December 10, 2020Applicant: SHINKAWA LTD.Inventors: Yasuyuki MATSUNO, Tomonori NAKAMURA, Shin TAKAYAMA, Hiroshi OMATA
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Patent number: 10847434Abstract: A method of manufacturing a semiconductor device in which a prescribed target lamination number of semiconductor chips are laminated on a substrate, the method includes: a first lamination step of laminating while temporarily bonding one or more semiconductor chips on the substrate to thereby form a first chip laminate body; a first permanent bonding step of pressurizing while heating from the upper side of the first chip laminate body to thereby collectively and permanently bond the one or more semiconductor chips; a second lamination step of sequentially laminating while temporarily bonding two or more semiconductor chips on the permanently bonded semiconductor chips to thereby form a second chip laminate body; and a second permanent bonding step of pressurizing while heating from the upper side of the second chip laminate body to thereby collectively permanently bond the two or more semiconductor chips.Type: GrantFiled: September 29, 2017Date of Patent: November 24, 2020Assignee: SHINKAWA LTD.Inventors: Tomonori Nakamura, Toru Maeda
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Publication number: 20200321311Abstract: A method of mounting a die includes: preparing a die having a bump formation surface on which a plurality of bump electrodes are formed; disposing a vacuum suction tool having a suction surface above the die such that the suction surface faces toward the bump formation surface; sandwiching a porous sheet between the suction surface and the bump formation surface and suctioning the die by the vacuum suction tool; and mounting the die that has been suctioned by the vacuum suction tool in a bonding region of a substrate with an adhesive material interposed therebetween, the porous sheet having a thickness equal to or greater than the protrusion height of the bump electrodes on the bump formation surface. Stabilization and ease of maintenance of vacuum suction can thereby be improved.Type: ApplicationFiled: May 30, 2017Publication date: October 8, 2020Applicants: SHINKAWA LTD., VALQUA, LTD.Inventors: Osamu WATANABE, Tomonori NAKAMURA, Yoshihito HAGIWARA, Yuji KANAI
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Publication number: 20200291548Abstract: A PTFE sheet in which PTFE fibers having a diameter of 1 ?m or less are spun, the PTFE sheet having a Gurley value in the range of 1 s/100 cc/in2 to 3 s/100 cc/in2 and a shrinkage factor in a direction orthogonal to a sheet winding direction of no more than 10% when heated to 300° C. The PTFE sheet makes a die adsorbable via a tool, which is for heating the die when the die is mounted on a mounting body, by being sandwiched between the die and the tool, and suppresses the adhesion, to an adsorption surface of the tool or to the die, of an adhesion member for fixing the die to the mounted body. Through this configuration, a PTFE sheet capable of stabilizing vacuum adsorption and improving maintainability and a method for mounting a die are provided.Type: ApplicationFiled: November 28, 2018Publication date: September 17, 2020Applicants: SHINKAWA LTD., VALQUA, LTD.Inventors: Osamu WATANABE, Tomonori NAKAMURA, Yoshihito HAGIWARA, Yuji KANAI
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Publication number: 20200286854Abstract: Provided is a method for setting the conditions for heating a semiconductor chip during bonding of the semiconductor chip using an NCF, wherein a heating start temperature and a rate of temperature increase are set on the basis of a viscosity characteristic map that indicates changes in viscosity with respect to temperature of the NCF at various rates of temperature increase and a heating start temperature characteristic map that indicates changes in viscosity with respect to temperature of the NCF when the heating start temperature is changed at the same rate of temperature increase.Type: ApplicationFiled: September 14, 2018Publication date: September 10, 2020Applicant: SHINKAWA LTD.Inventors: Tomonori NAKAMURA, Toru MAEDA, Satoru NAGAI, Yoshihiro SAEKI, Osamu WATANABE
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Publication number: 20200286852Abstract: The apparatus which assists in deriving bonding conditions includes a bonding unit which bonds a semiconductor chip and a substrate by applying heat and pressure with NCF interposed therebetween, a library in which a variety of physical property information including viscosity characteristic information is collected with respect to each of a plurality of types of NCFs, an initial evaluation condition determination unit which acquires the physical property information corresponding to the NCF used for bonding with reference to the library and determines an initial value of an evaluation condition of bonding evaluation performed by bonding the semiconductor chip and the substrate, and a bonding evaluation unit which drives the bonding unit in accordance with set evaluation condition, bonds the semiconductor chip and the substrate and performs the bonding evaluation at least once to measure the viscosity of the NCF at the time of the bonding.Type: ApplicationFiled: March 5, 2020Publication date: September 10, 2020Applicant: SHINKAWA LTD.Inventor: Tomonori Nakamura
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Publication number: 20200258794Abstract: There is provided a semiconductor manufacturing method capable of coping with an increase in the density of an integrated circuit. A semiconductor manufacturing method according to one aspect of the present invention includes: a step of forming a memory cell, a photodiode that outputs an electrical signal corresponding to an input optical signal, and a signal processing circuit that generates a logic signal based on the electrical signal output from the photodiode and outputs the logic signal to the memory cell, so as to correspond to each chip forming region of a wafer having a plurality of chip forming regions; a step of inputting pump light for checking an operation of the memory cell to the photodiode and inspecting an operation state of the memory cell after the forming step; and a step of performing dicing for each of the chip forming regions after the inspection step.Type: ApplicationFiled: June 13, 2018Publication date: August 13, 2020Applicant: HAMAMATSU PHOTONICS K.K.Inventors: Tomonori NAKAMURA, Motohiro SUYAMA, Hironori TAKAHASHI
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Publication number: 20200251441Abstract: The mounting apparatus includes: a bonding head 14 that bonds, while pressing, a semiconductor chip 100 onto a substrate 110 or another semiconductor chip 100; and a heating mechanism 16 that heats the semiconductor chip 100 from the side during the execution of this bonding. After two or more semiconductor chips 100 are stacked while being bonded by temporary pressure-bonding, the bonding head 14 heats and applies pressure to an upper surface of the resultant stacked body, thereby integrally pressure-bonding the two or more semiconductor chips 100, and at the time of this pressure-bonding the heating mechanism 16 heats the stacked body from the side.Type: ApplicationFiled: January 30, 2018Publication date: August 6, 2020Applicant: SHINKAWA LTD.Inventors: Yoshihito HAGIWARA, Tomonori NAKAMURA, Hiroshi HORIBE
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Publication number: 20200243476Abstract: A bonding apparatus bonds a semiconductor die, which has a first mam surface provided with a bump electrode, to a substrate by means of thermo-compression, with a thermo-compression film being interposed therebetween. The bonding apparatus includes: an intermediate stage that has a die placing surface on which the semiconductor die is placed such that the die placing surface faces the first main surface; and a bonding tool which detachably holds a second main surface of the semiconductor die that is placed on the intermediate stage, the second main surface being on the reverse side of the first main surface. The intermediate stage has a push-up mechanism which applies, to the first main surface of the semiconductor die, a force for separating the semiconductor die therefrom in the normal direction of the die placing surface (in a Z-axis direction).Type: ApplicationFiled: May 18, 2018Publication date: July 30, 2020Applicant: SHINKAWA LTD.Inventors: Tetsuya OTANI, Osamu WATANABE, Tomonori NAKAMURA
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Publication number: 20200243356Abstract: A mounting apparatus for manufacturing a semiconductor device by bonding a semiconductor chip (12) to a mounted object that is a substrate (30) or another semiconductor chip (12) is provided. The mounting apparatus includes: a stage (120) on which the substrate (30) is placed, a mounting head (124) that is capable of moving relative to the stage (120) and bonds the semiconductor chip (12) to the mounted object, and an irradiation unit (108 that irradiates, from a lower side of the stage (120), an electromagnetic wave transmitting through the stage and heating the substrate (30). The stage (120) has a first layer (122) formed on an upper surface side, and the first layer (122) has a greater thermal resistance in a plane direction than the thermal resistance in a thickness direction.Type: ApplicationFiled: May 29, 2018Publication date: July 30, 2020Applicant: SHINKAWA LTD.Inventors: Tomonori NAKAMURA, Toru MAEDA, Tetsuo TAKANO
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Publication number: 20200241054Abstract: An image generating device is an apparatus for acquiring an image which shows a direction of an electric current flowing through a semiconductor device. The image generating device comprises a signal application unit configured to apply a stimulation signal to the semiconductor device, a magnetic detection unit configured to output a detection signal based on a magnetism generated by an application of the stimulation signal, and an image generation unit configured to generate phase image data comprising a phase component which indicates a phase difference based on the phase difference between the detection signal and a reference signal which is generated based on the stimulation signal and generate an electric current direction image which shows the direction of the electric current based on the phase image data.Type: ApplicationFiled: April 7, 2020Publication date: July 30, 2020Applicant: HAMAMATSU PHOTONICS K.K.Inventors: Akihiro OTAKA, Tomonori NAKAMURA
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Publication number: 20200241275Abstract: An optical device for microscopic observation 4 comprises: a cold stop 13 having openings 13d, 13e corresponding to a low-magnification microscope optical system 5 and being a stop member arranged in a vacuum vessel 12 to let the light from the sample S pass to the camera 3; a warm stop 10 having an opening 14 corresponding to a high-magnification microscope optical system 5 and being a stop member arranged outside the vacuum vessel 12 to let the light from the sample S pass toward the cold stop 13; and a support member 11 supporting the warm stop 10 so that the warm stop can be inserted to or removed from on the optical axis of the light from the sample S, wherein the warm stop 10 has a reflective surface 15 on the camera 3 side and wherein the opening 14 is smaller than the openings 13d, 13e.Type: ApplicationFiled: April 17, 2020Publication date: July 30, 2020Applicant: HAMAMATSU PHOTONICS K.K.Inventors: Tomonori Nakamura, Ikuo Arata, Yoshihiro Ito
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Publication number: 20200235070Abstract: A mounting apparatus for stacking and mounting two or more semiconductor chips at a plurality of locations on a substrate includes: a first mounting head for forming, at a plurality of locations on the substrate, temporarily stacked bodies in which two or more semiconductor chips are stacked in a temporarily press-attached state; and a second mounting head for forming chip stacked bodies by sequentially finally press-attaching the temporarily stacked bodies formed at the plurality of locations. The second mounting head includes: a press-attaching tool for heating and pressing an upper surface of a target temporarily stacked body to thereby finally press-attach the two or more semiconductor chips configuring the temporarily stacked body altogether; and one or more heat-dissipation tools having a heat-dissipating body which, by coming into contact with an upper surface of another stacked body positioned around the target temporarily stacked body, dissipates heat from the another stacked body.Type: ApplicationFiled: January 30, 2018Publication date: July 23, 2020Applicant: SHINKAWA LTD.Inventors: Tomonori NAKAMURA, Toru MAEDA
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Patent number: 10705139Abstract: A semiconductor device inspection system (1) includes a laser beam source (2), for emitting light, an optical sensor (12) for detecting the light reflected by the semiconductor device (10) from the light and outputting a detection signal, a frequency band setting unit (16) for setting a measurement frequency band and a reference frequency band with respect to the detection signal, a spectrum analyzer (15) for generating a measurement signal and a reference signal from the detection signals in the measurement frequency band and the reference frequency band, and a signal acquisition unit (17) for calculating a difference between the measurement signal and the reference signal to acquire an analysis signal. The frequency band setting unit (16) sets the reference frequency band to a frequency domain in which a level of the detection signal is lower than a level obtained by adding 3 decibels to a white noise level serving as a reference.Type: GrantFiled: July 9, 2018Date of Patent: July 7, 2020Assignee: HAMAMATSU PHOTONICS K.K.Inventor: Tomonori Nakamura
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Patent number: 10698006Abstract: An inspection apparatus includes a tester unit that applies a stimulus signal to a semiconductor apparatus, an MO crystal arranged to face a semiconductor apparatus, a light source that outputs light, an optical scanner that irradiates the MO crystal with light output from light source, a light detector that detects light reflected from the MO crystal arranged to face the semiconductor apparatus D and outputs a detection signal, and a computer that generate phase image data based on a phase difference between a reference signal generated based on a stimulus signal and the detection signal, the phase image data including a phase component indicating the phase difference, and generates an image indicating a path of a current from the phase image data.Type: GrantFiled: February 2, 2016Date of Patent: June 30, 2020Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Tomonori Nakamura, Akihiro Otaka
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Publication number: 20200176339Abstract: There is provided a semiconductor wafer suitable for the inspection of an operation state. A wafer is a semiconductor wafer having a plurality of chip forming regions, and includes a memory cell that is formed in each of the chip forming regions and an inspection device that is formed outside each of the chip forming regions. The inspection device has a photodiode that receives an input of pump light for checking an operation of the memory cell and outputs an electrical signal corresponding to the pump light and a signal processing circuit that generates a logic signal based on the electrical signal output from the photodiode and outputs the logic signal to the memory cell.Type: ApplicationFiled: June 13, 2018Publication date: June 4, 2020Applicant: HAMAMATSU PHOTONICS K.K.Inventors: Motohiro SUYAMA, Hironori TAKAHASHI, Tomonori NAKAMURA
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Publication number: 20200174074Abstract: There is provided a semiconductor wafer suitable for the inspection of an operation state. A wafer is a semiconductor wafer having a plurality of chip forming regions, and includes a memory cell that is formed in each of the chip forming regions and an inspection device that is formed in each of the chip forming regions. The inspection device has a photodiode that receives an input of pump light for checking an operation of the memory cell and outputs an electrical signal corresponding to the pump light and a signal processing circuit that generates a logic signal based on the electrical signal output from the photodiode and outputs the logic signal to the memory cell.Type: ApplicationFiled: June 13, 2018Publication date: June 4, 2020Applicant: HAMAMATSU PHOTONICS K.K.Inventors: Motohiro SUYAMA, Hironori TAKAHASHI, Tomonori NAKAMURA
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Patent number: 10663709Abstract: An optical device for microscopic observation 4 comprises: a cold stop 13 having openings 13d, 13e corresponding to a low-magnification microscope optical system 5 and being a stop member arranged in a vacuum vessel 12 to let the light from the sample S pass to the camera 3; a warm stop 10 having an opening 14 corresponding to a high-magnification microscope optical system 5 and being a stop member arranged outside the vacuum vessel 12 to let the light from the sample S pass toward the cold stop 13; and a support member 11 supporting the warm stop 10 so that the warm stop can be inserted to or removed from on the optical axis of the light from the sample S, wherein the warm stop 10 has a reflective surface 15 on the camera 3 side and wherein the opening 14 is smaller than the openings 13d, 13e.Type: GrantFiled: July 2, 2018Date of Patent: May 26, 2020Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Tomonori Nakamura, Ikuo Arata, Yoshihiro Ito
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Patent number: 10656187Abstract: An image generating device is an apparatus for acquiring an image which shows a direction of an electric current flowing through a semiconductor device. The image generating device comprises a signal application unit configured to apply a stimulation signal to the semiconductor device, a magnetic detection unit configured to output a detection signal based on a magnetism generated by an application of the stimulation signal, and an image generation unit configured to generate phase image data comprising a phase component which indicates a phase difference based on the phase difference between the detection signal and a reference signal which is generated based on the stimulation signal and generate an electric current direction image which shows the direction of the electric current based on the phase image data.Type: GrantFiled: September 5, 2016Date of Patent: May 19, 2020Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Akihiro Otaka, Tomonori Nakamura