Patents by Inventor Tomoyuki Yamada

Tomoyuki Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100078128
    Abstract: A gas flow of a gas pipe is indicated before an electromagnetic valve is actually opened, so that the electromagnetic valve can be prevented from being opened or closed by a wrong manipulation or hazards caused by undesired mixing of gases can be avoided so as to improve safety. The substrate processing apparatus includes a state detection unit configured to detect an opening/closing request state and an opening/closing state of a valve installed at a gas pipeline; and a indication unit configured to indicate a gas flow state of the gas pipeline predicted according to the opening/closing request state and a gas flow state of the gas pipeline when the valve is opened, in a way that each state is distinguished.
    Type: Application
    Filed: September 28, 2009
    Publication date: April 1, 2010
    Inventors: Tomoyuki YAMADA, Mamoru Oishi, Kanako Kitayama
  • Publication number: 20090283791
    Abstract: A lead frame (100) for a semiconductor device is formed by applying nickel plating (102), palladium plating (103), and gold flash plating (104) substantially entirely to lead frame body (101) such as copper thin plate in this order, and further applying silver plating (105) selectively to part of an inner part that is to be enclosed with a package of the semiconductor device. The lead frame (100) may also include a base of the package. The silver plating contributes to an excellent light reflectance and wire bonding efficiency of the inner part, whereas the gold flash plating contributes to an excellent resistance to corrosion and soldering efficiency of an outer part that is outside the package.
    Type: Application
    Filed: July 24, 2009
    Publication date: November 19, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Hidekazu TOMOHIRO, Masayuki Fujii, Norio Satou, Tomoyuki Yamada, Tomio Kusano
  • Publication number: 20090263084
    Abstract: Two AWG circuits are integrated while preventing degradation in quality of a multiplexing/demultiplexing function. An arrayed waveguide grating circuit includes: a first slab waveguide (52) connected to a first input waveguide (51a) and second output waveguides (55b); a second slab waveguide (54) connected to first output waveguides (55a) and a second input waveguide (51b); and an array waveguide (53) connecting the first slab waveguide (52) and the second slab waveguide (54), wherein the input waveguides (51a, 51b) are connected to the slab waveguides (52, 54) at an interval of 1.5× from the outermost second output waveguide out of the second output waveguides (55a, 55b) connected at an interval x depending on a wavelength.
    Type: Application
    Filed: December 21, 2006
    Publication date: October 22, 2009
    Applicants: Nppon Telegraph and Telephone Corporation, NTT Electronics Corportion
    Inventors: Tomoyuki Yamada, Mitsuru Nagano, Mikitaka Ito, Toshio Watanabe, Takayuki Mizuno, Takashi Goh, Akimasa Kaneko
  • Patent number: 7573279
    Abstract: A jig for Kelvin Test includes a first probe and a second probe which are arranged in parallel in a socket comprised of insulating material. Probes include a conductive tube and a conductive plunger, contained in at least one end side of the tube, and having a distal end part protruding axially outward from the tube. The tube contains a coil spring adapted to elastically urge the plunger outward. The first probe is used for supplying electric current to a terminal of an electronic component to be tested. The second probe is used for monitoring electric voltage of the terminal. A first cross section of the tube of the first probe which is perpendicular to the axial direction is greater than a second cross section of the tube of the second probe which is perpendicular to the axial direction. The plunger is brought into elastic contact with the terminal.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: August 11, 2009
    Assignee: Yokowo Co., Ltd.
    Inventors: Tomoyuki Yamada, Satoshi Kakegawa
  • Publication number: 20090197402
    Abstract: In a substrate processing apparatus, a process vessel is configured to accommodate and process a substrate held at a horizontal position. A gas introduction port is installed at a periphery of a first side of the process vessel and configured to introduce gas into the process vessel from a lateral direction of the substrate. A gas exhaust port is installed at a second side of the process vessel which is opposite to the first side, and is configured to exhaust gas inside the process vessel from a lateral direction of the substrate. A slope part is installed between the gas introduction port and the gas exhaust port inside the process vessel, and is configured to guide a flow path of the gas introduced into the process vessel.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 6, 2009
    Inventors: Seiyo NAKASHIMA, Tomoyuki Yamada, Masakazu Shimada
  • Publication number: 20090192652
    Abstract: Provided is a substrate processing apparatus which is capable of detecting malfunction of mechanisms installed inside MFC. An inert gas supply line (308) for supplying an inert gas, a first shut-off valve (300) for shutting off the supply of the inert gas, a process gas supply line (310) for supplying a process gas, and a second shut-off valve (302) for shutting off the supply of the process gas are installed at the upstream side of the MFC (241). A gas supply pipe (232) connected to a process chamber (210), a third shut-off valve (304) for shutting off the supply of gas to the gas supply pipe (232), an exhaust vent line (318) which is exhaustible, a fourth shut-off valve (306) for shutting off the supply of gas to the exhaust vent line (318) are installed at the downstream side of the MFC (241).
    Type: Application
    Filed: October 29, 2008
    Publication date: July 30, 2009
    Inventor: Tomoyuki YAMADA
  • Publication number: 20090037855
    Abstract: A simulation method to be implemented in a computer causes the computer to execute a procedure carrying out a weighting with respect to layout parameters of a circuit, which is an analyzing target, based on priority information of cells forming the circuit, and converting the weighted layout parameters into physical characteristics and storing the physical characteristics in a memory part, a procedure converting the physical characteristic read from the memory part into circuit parameters and storing the circuit parameters into the memory part, and analyzing the circuit based on a net list including the circuit parameters read from the memory part.
    Type: Application
    Filed: April 29, 2008
    Publication date: February 5, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Yusuke TANEFUSA, Norihiro HARADA, Tsuyoshi SAKATA, Tomoyuki YAMADA
  • Publication number: 20080263002
    Abstract: An apparatus, method, etc. that in designing of the base sequence of, for example, siRNA, realize high-speed retrieval any genes containing analogous base sequences without omission. Accordingly, retrieval is carried out in such a manner that two partial sequences of given length and any extra part are identified from inputted base sequences, and that hamming distance being the number of corresponding bases incompatible with each other is divided and assigned to the partial sequences and extra part and out of the two partial sequences, one with an assigned number not greater is selected and retrieved.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 23, 2008
    Inventors: Shinichi Morishita, Tomoyuki Yamada
  • Patent number: 7438245
    Abstract: Disclosed is a milling and classifying apparatus, adapted to produce toner fine particles, comprising a collision mill, and an air classifier, wherein the collision mill comprises a jet nozzle room, a path, a collision plate, and a collision member mounted to a support of the collision plate at downstream of the collision plate, the air classifier comprises a dispersion room and a classification room, the classification room is disposed below the dispersion room, and a flow stabilizer is arranged at a central suction of the separator core to control swirl stream generated within the classification room so as to centrifuge the powder into coarse particles and fine particles by action of the swirl stream.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: October 21, 2008
    Assignee: Ricoh Company, Ltd.
    Inventors: Masahiro Kawamoto, Kohta Wakimoto, Kohji Kubota, Mamoru Kawaguchi, Yoshiyuki Okegawa, Hideyuki Ueda, Masayuki Kakimoto, Hiroaki Sugiyama, Tomoyuki Yamada, Yuuichi Kohyama, Masato Kobayashi, Fumio Nishide, Kenkoh Degura, Hirofumi Yamanaka, Tohru Suganuma, Shoji Watanabe, Ikuo Tasaki
  • Publication number: 20080230874
    Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.
    Type: Application
    Filed: March 24, 2008
    Publication date: September 25, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki YAMADA, Fumio USHIDA, Shigetoshi TAKEDA, Tomoharu AWAYA, Koji BANNO, Takayoshi MINAMI
  • Publication number: 20080226290
    Abstract: By reducing the number of PD arrays, and by simplifying the configuration of an optical power monitor in a WDM system, a miniaturized, cost reduced optical signal monitoring apparatus, optical system or optical signal monitoring method is provided. An optical power monitor 1 has an optical switch 30 having four input ports 31, a DMUX 2 having 48 output ports, and six CSP type PD array modules 50 each including an 8-channel PD array. The output port 32 of the optical switch 30 having four switchable input ports 31 is optically connected to the input port 21 of the AWG 20. The 48 output ports 22 of the AWG 20 are each optically connected to photosensitive surfaces 53 of the individual PDs included in the CSP type PD array modules 50. The CSP type PD array modules 50 are mounted on the end face of the AWG 20.
    Type: Application
    Filed: March 5, 2008
    Publication date: September 18, 2008
    Applicants: Nippon Telegraph and Telephone Corporation, NTT Electronics Corporation
    Inventors: Takaharu Ohyama, Takashi Goh, Shin Kamei, Shunichi Sohma, Mikitaka Itoh, Ikuo Ogawa, Akimasa Kaneko, Tomoyuki Yamada, Mitsuru Nagano, Yoshiyuki Doi, Takashi Saida
  • Publication number: 20080153314
    Abstract: An object of the present invention is to improve substrate processing efficiency. A substrate processing apparatus has a reaction tube that processes a substrate inside, and a heating apparatus disposed so as to surround an external periphery of the reaction tube, so that at least a gas inlet tube is disposed on a side surface in an area in which the substrate is processed inside the reaction tube, and the heating apparatus has a heat insulator that surrounds the reaction tube, an inlet opening formed in the shape of a groove in the heat insulator from the lower end of the heating apparatus so as to avoid the gas inlet tube, and a heating element disposed between the heat insulator and the reaction tube.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 26, 2008
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Akira Hayashida, Masaaki Ueno, Masakazu Shimada, Yukinori Aburatani, Tomoyuki Yamada, Sieyo Nakashima, Masashi Sugishita
  • Publication number: 20080083973
    Abstract: There is provided a lead frame for an optical semiconductor device, an optical semiconductor device using such lead frame, and a manufacturing method for these, where the optical semiconductor device exhibits favorable brightness over a long period of time by preventing discoloration and degeneration of a plating layer provide on the lead frame and a resulting reduction in a reflection coefficient for light emitted from a light emitting element, even when using silicone resin as a sealing resin. An Ag—Au alloy plating layer 22 is formed on the surface of a pure Ag plating layer 21 on a lead frame 10 sealed chloroplatinic acid-containing silicon resin, so as to prevent direct contact between the layer 21 and the silicone resin. This suppresses the formation of AgCl due to a reaction with a hardening catalyst of the silicon resin, thereby preventing the Ag plating layer from turning a blackish-brown color.
    Type: Application
    Filed: March 7, 2007
    Publication date: April 10, 2008
    Inventors: Tomoyuki Yamada, Tomohiro Futagami, Keishiro Kawano
  • Patent number: 7340701
    Abstract: There is provided a layout verification method including a space acquisition step of, with a wiring connected to a gate through a via as a target wiring, acquiring a space between the target wiring and a wiring adjacent thereto, a calculation step of calculating an antenna ratio according to the space between the target wiring and the adjacent wiring, the area of the gate, and the area of the target wiring, and an output step of outputting an antenna damage error when the antenna ratio exceeds a predetermined value.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: March 4, 2008
    Assignee: Fujitsu Limited
    Inventor: Tomoyuki Yamada
  • Publication number: 20080042676
    Abstract: A jig for Kelvin Test, includes: a pair of probes, including a first probe and a second probe which are arranged in parallel in a socket comprised of insulating material, each probe including: an conductive tube; an conductive plunger, contained in at least one end side of the tube, and having a distal end part protruding outward from the tube in an axial direction of the tube, the plunger adapted to be brought into elastic contact with a terminal of an electronic component to be tested, and a coil spring, contained in the tube, and adapted to elastically urge the plunger outward. The first probe is used for supplying electric current to the terminal. The second probe is used for monitoring electric voltage of the terminal. A first cross section of the tube of the first probe which is perpendicular to the axial direction is greater than a second cross section of the tube of the second probe which is perpendicular to the axial direction.
    Type: Application
    Filed: August 14, 2007
    Publication date: February 21, 2008
    Inventors: Tomoyuki Yamada, Satoshi Kakegawa
  • Publication number: 20070202504
    Abstract: It is intended to efficiently determine a base sequence specifically appearing in an expression gene. For this, providing that the expression gene consists of exons (301) . . . (306) and especially that exon (301) is united with exon (302) and exon (302) with exon (303), an aggregate of base sequences (401) (403) being a union of exon base sequences (301) . . . (305) and a boundary base sequence obtained by uniting together base sequences (404) and (405) and base sequences (406) and (407) respectively existing over boundaries between exon (301) and exon (302) and between exon (302) and exon (303) is formed, and the aggregate is searched. If a base sequence is one specifically appearing in the expression gene, the number of search results is 1 and otherwise, the number is plural.
    Type: Application
    Filed: March 23, 2005
    Publication date: August 30, 2007
    Inventors: Shinichi Morishita, Tomoyuki Yamada, Yuki Naito
  • Publication number: 20060102936
    Abstract: A lead frame (100) for a semiconductor device is formed by applying nickel plating (102), palladium plating (103), and gold flash plating (104) substantially entirely to lead frame body (101) such as copper thin plate in this order, and further applying silver plating (105) selectively to part of an inner part that is to be enclosed with a package of the semiconductor device. The lead frame (100) may also include a base of the package. The silver plating contributes to an excellent light reflectance and wire bonding efficiency of the inner part, whereas the gold flash plating contributes to an excellent resistance to corrosion and soldering efficiency of an outer part that is outside the package.
    Type: Application
    Filed: January 13, 2004
    Publication date: May 18, 2006
    Inventors: Hidekazu Tomohiro, Masayuki Fujii, Norio Satou, Tomoyuki Yamada, Tomio Kusano
  • Publication number: 20060064657
    Abstract: There is provided a layout verification method including a space acquisition step of, with a wiring connected to a gate through a via as a target wiring, acquiring a space between the target wiring and a wiring adjacent thereto, a calculation step of calculating an antenna ratio according to the space between the target wiring and the adjacent wiring, the area of the gate, and the area of the target wiring, and an output step of outputting an antenna damage error when the antenna ratio exceeds a predetermined value.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 23, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Tomoyuki Yamada
  • Publication number: 20060032952
    Abstract: Disclosed is a milling and classifying apparatus, adapted to produce toner fine particles, comprising a collision mill, and an air classifier, wherein the collision mill comprises a jet nozzle room, a path, a collision plate, and a collision member mounted to a support of the collision plate at downstream of the collision plate, the air classifier comprises a dispersion room and a classification room, the classification room is disposed below the dispersion room, and a flow stabilizer is arranged at a central suction of the separator core to control swirl stream generated within the classification room so as to centrifuge the powder into coarse particles and fine particles by action of the swirl stream.
    Type: Application
    Filed: July 12, 2005
    Publication date: February 16, 2006
    Inventors: Masahiro Kawamoto, Kohta Wakimoto, Kohji Kubota, Mamoru Kawaguchi, Yoshiyuki Okegawa, Hideyuki Ueda, Masayuki Kakimoto, Hiroaki Sugiyama, Tomoyuki Yamada, Yuuichi Kohyama, Masato Kobayashi, Fumio Nishide, Kenkoh Degura, Hirofumi Yamanaka, Tohru Suganuma, Shoji Watanabe, Ikuo Tasaki
  • Publication number: 20050071089
    Abstract: It is intended to support a unique design of a primer. To calculate an indication showing the occurrence frequency of a sequence in a genome sequence, the occurrence frequencies of partial sequences having a definite length in the genome sequences are calculated. Then the occurrence of frequency of each partial sequence of the definite length is stored in an incidence/isolation degree table (16). Concerning each partial sequence of the definite length, a degree of isolation i, which means that j mutation indicating the conversion of j bases (j=<i?1) does not occur in the genome sequence but i mutation indicating the conversion of i bases occurs in the genome sequence, is calculated. Then the degrees of isolation of the partial sequences of the definite length are stored in the incidence/isolation degree table (16).
    Type: Application
    Filed: December 27, 2002
    Publication date: March 31, 2005
    Inventors: Shinichi Morishita, Tomoyuki Yamada