Abstract: A system and method for processing an image of a retail shelf area. According to one aspect, a portion of an image that depicts the retail shelf area at an angled and depthwise perspective is determined to depict shelves. The image can be modified so that the portion of the image determined to depict shelves is substantially parallel to a predefined horizontal reference frame. Products can then be detected in the remainder portion of the image, separate from the portion of the image determined to depict shelves. An applicable planogram can be used to generate compliance information based on the detected products and the determined portion of the image depicting shelves.

Abstract: A device for detecting a concentration of tiny particulates in an air sample is provided. The device comprises: a container that contains the air sample and has an opening; a sealing mechanism that opens or seals the opening; a sensor provided in the container and operative to sense a total concentration of particulates in the air sample within the container; and a controller connected to the sensor and operative to control the sealing mechanism.

Abstract: The present disclosure provides a management apparatus and a method for wireless communication as well as an apparatus and a method for wireless communication. The management apparatus includes: a determining module, configured to select a communication unit satisfying a predetermined condition from among a communication unit cluster managed by the management apparatus, and determine interference information or load information of at least part of resource blocks corresponding to the communication unit.

Abstract: Embodiments of the disclosure provide a shift register, a driving method and a gate driving circuit. In an embodiment, the shift register includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first storage capacitor and a second storage capacitor. The shift register is driven by the cooperation of the respective transistors. In the case that the shift register is applied in the gate driving circuit to implement a line-by-line scanning, shift registers corresponding to two adjacent pixel rows are cascaded directly and no inverters are provided following the shift registers corresponding to the respective pixel rows, thereby decreasing the number of transistors in the gate driving circuit, reducing the layout area of the gate driving circuit, and being advantageous for narrowing the border.

Abstract: A method for processing payment transactions with merchant-specific fraud detection includes: storing a merchant profile, the profile including data related to a merchant including a merchant identifier and a plurality of transaction data entries, each entry including data related to a payment transaction involving the merchant including transaction data; receiving an authorization request for a payment transaction, the request including the merchant identifier and transaction data; calculating a fraud score for the payment transaction based on application of one or more scoring algorithms to the transaction data included in the authorization request and based on the transaction data included in transaction data entries in the merchant profile; transmitting the transaction data included in the received authorization request and the calculated fraud score to the merchant; and receiving a notification from the merchant indicating acceptance of risk for the payment transaction.

Abstract: A method and a system are provided determining affiliation of foreign payment card holders (e.g., students) with domestic educational institutions (e.g., universities and colleges). In particular, the present disclosure provides a method and a system for assessing the relative degree of proximity of the residential geolocation of the foreign payment card holders and the geolocation of the domestic educational institutions to facilitate determining whether the foreign payment card holders are affiliated with the domestic educational institutions, and also for assessing purchasing and payment behavior of the foreign payment card holders at domestic merchants. Predictive behavioral profiles are generated based on the purchasing and payment activities and shopping patterns of the foreign payment card holders by date at the domestic merchants, and the relative degree of proximity of the residential geolocation of the foreign payment card holders with the geolocation of the domestic educational institutions.

Abstract: A portable tennis apparatus comprising a tennis bag, a tennis ball retrieving unit, a stretchable back bar and an extendable bottom stand. The ball retrieving unit retrieves balls on the ground directly to the bag; the stretchable back bar can be pulled up and pushed around with rolling means on the ground easily. The top opening of the bag made it easy to reach the balls for replay. The extendable stand can raise the tennis bag at a desirable level for dispensing balls so that the player does not have to bend down. The stretchable back bar and the stand can be put back to their original position during the transportation of the apparatus, such as between tennis court and player's home. The entire apparatus is light-weighted, easily carried and operated single-handed. This apparatus is truly an “all-in-one” tennis apparatus, and a revolution in the field of tennis equipment.

Abstract: Disclosed is a membrane surface modification method. The method is applicable to a variety of hydrophobic membranes by doping selected inorganic particles. One act of the method involves the in-situ embedment of the inorganic particles onto the membrane surface by dispersing the particles in a non-solvent bath for polymer precipitation. Further membrane surface modification can be achieved by hydrothermally growing new inorganic phase on the embedded particles. The embedment of particles is for the subsequent phase growth.

Abstract: A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.

Abstract: A method and system for evaluating a card-present payment card transaction for fraud using a computer device coupled to a database are provided. The method includes determining a home activity region for a cardholder using payment card transaction data for the cardholder, receiving a payment card transaction authorization request, and determining a payment card activity location of the received payment card transaction authorization request. The method also includes comparing the determined payment card activity location to the determined home activity region, determining if the determined payment card activity location is within the determined home activity region using a at least one of a selectable threshold and a determined threshold, and outputting a score for the received payment card transaction authorization request based on the determination of whether the payment card activity location is within the determined home activity region.

Abstract: A system and method of providing direct data access between a non-volatile cache and a NIC in a computing system. A system is disclosed that includes a processing core embedded in a controller that controls a non-volatile cache; and a direct access manager for directing the processing core, wherein the direct access manager includes: a switch configuration system that includes logic to control a switch for either a remote direct access mode or a host access mode, wherein the switch couples each of the NIC, a local bus, and the non-volatile cache; a command processing system that includes logic to process data transfer commands; and a data transfer system that includes logic to manage the flow of data directly between the non-volatile cache and the NIC.

Abstract: A system, method and program product for transferring contiguous blocks of data between a host storage and a flash memory. A method is disclosed that includes: receiving from a host at a flash controller a host command that specifies a contiguous set of LBAs and specifies a corresponding sub-section of an LBA to PBA mapping table; fetching the sub-section of the LBA to PBA mapping table from the host and storing the sub-section in a sub-mapping table; and for each LBA in the contiguous set of LBAs, performing a look-up into the sub-mapping table to retrieve a corresponding PBA and using the corresponding PBA to effectuate a data transfer between the host and flash memory from the flash controller.

Abstract: Systems and methods associated with dynamic face identification are disclosed. One example method includes matching a query face against a set of clusters in a dynamic collection. Matching the query face against the set of clusters may facilitate identifying a person associated with the query face. The example method also includes matching the query face against a set of images in a static gallery to identify the person. Matching the query face against the static gallery may be performed when matching the query face against the set of clusters fails to identify the person. The example method also includes updating the set of clusters in the dynamic collection using the query face.

Abstract: A system and method of providing in-memory data processing for object-oriented data with a flash memory storage. A system is disclosed that includes: a first logic process for providing intra-object data processing involving a single data object with an expansion factor greater than one; a second logic process for providing intra-object data processing involving a single data object with an expansion factor less than one; and a third logic process for providing inter-object data processing involving multiple objects.

Abstract: A storage infrastructure, device and associated method for storing compressed data is provided. Included is a method for compressing data on a storage device in a storage infrastructure, including: receiving a compressed extent from a host, wherein the compressed extent includes data compressed with entropy-coding-less data compression; receiving logical identification information about the compressed extent from the host; performing in-memory entropy encoding on the compressed extent to generate a compressed unit; storing the compressed unit in a physical memory; and in a case where the host is aware of the in-memory entropy encoding, reporting size information of the compressed unit back the host.

Abstract: A system and method of providing direct data access between a non-volatile cache and a set of storage devices in a computing system. A system is disclosed that includes: a processing core embedded in a controller card that controls a non-volatile cache system; and a direct access manager for directing the processing core, wherein the direct access manager includes: a switch configuration system that includes logic to control a switch for either a direct access mode or a CPU access mode, wherein the switch couples each of the storage devices, a local bus, and the non-volatile cache system; a command output system that includes logic to output data transfer commands; and a data transfer system that includes logic to manage the flow of data directly between the non-volatile memory and the set of storage devices; and an arbitrator that arbitrates data traffic flow through the switch.

Abstract: Technologies are generally described for systems, devices and methods effective to reduce power consumption in flash memory. In some examples, a bit error rate estimator module may estimate two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. A voltage setup module may be configured to be in communication with the bit error rate estimator module. The voltage setup module may be configured to select a voltage to read from the memory. The voltage may be selected based on the two or more bit error rates and based on an error correction level. The error correction level may be a tolerance level available to correct read errors from the memory.

Abstract: A method and system for clustering images, comprising detecting faces in respective images to generate face data, generating a first cluster of images using the face data, the first cluster comprising images with a common face and representing a corresponding person, generating a second cluster of images using clothes data representing a set of clothing signatures, the second cluster comprising images with a common set of clothes, and using the first and second clusters to link an image of the person to the clusters in order to generate a third cluster for the person.

Abstract: An inverter includes first, second, third, fourth, and fifth transistors, and first and second capacitors. The transistors and capacitors are connected in such way that the reverse conduction of the second transistor is prevented through controlling the gate electrode of the second transistor and maintaining the electrical potential at the gate electrode of the fifth transistor by the second capacitor. The electrical potential at the gate electrode of the fifth transistor is maintained stable when a first clock signal changes from high to low (when the first to fifth transistors are NMOS transistors) or from low to high (when the first to fifth transistors are PMOS transistors), so that the output signal of the inverter may not be affected by a change of the first clock signal, thus enabling the inverter to generate a stable output signal and a display panel comprising the inverter to obtain a better display effect.

Abstract: Technologies are generally described for systems, devices and methods relating to generation of an instruction to store data. Read unit length information may be identified for data. The read unit length information may include a read unit length. The data may have a data length. The data length may implicate a first error correction code of a first size. The read unit length may relate to an amount of the data to be read as a unit from a memory. The read unit length may be different from the data length. A second error correction code may be determined to store the data. The second error correction code may be based on the read unit length information. The second error correction code may have a second size. The instruction may be effective to store the second error correction code in association with the data in a memory.