Abstract: In a signal electric potential conversion circuit, a capacitor has one end receiving an input signal CIN, and the other end connected to a termination node N1. A conversion circuit receives a potential IN of the termination node N1. A connection element is provided between a power supply VDDH and the termination node N1, and an impedance of the connection element is reduced when the potential IN is lower than a first potential. Another connection element is provided between the termination node N1 and a ground power supply, and an impedance of the connection element is reduced when the potential IN is higher than a second potential.

Abstract: An interchannel skew adjustment circuit adjusts signal skew between a first channel and a second channel. The circuit includes a phase adjustment circuit configured to receive a signal of the first channel, delay the signal by a discretely variable delay amount, and output a delayed signal; a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of the second channel, and detect a phase difference between these two signals; and a controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit. This interchannel skew adjustment circuit adjusts the interchannel signal skew only at a sender or a receiver, thereby reducing the circuit area and the power consumption.

Abstract: In an input protection circuit, one end of a resistive element of a protection circuit is connected to an intermediate impedance point of a terminating device, which is connected between a pair of external terminals of a low amplitude differential interface circuit. The other end of the resistive element is connected to an anode terminal of a diode element. A cathode terminal of the diode element is connected to a reference potential terminal. As a result, even when one of external terminals of a low-breakdown voltage circuit is erroneously in contact with a signal terminal (i.e., a bus terminal which is always pulled up via a high resistance resistor) of the socket to be pulled up to a high voltage, the elements forming the circuit are greatly protected from deterioration and damages at low costs, while maintaining the quality of transmission signals.

Abstract: There is provided a ferrite core material for an electrophotographic developer, the ferrite core material having a ferrite particle composition represented by the formula (1) shown below, containing SrO replacing a part of (MnO) and/or (MgO) in the formula (1) shown below, and having a Cl concentration of 0.1 to 100 ppm, as measured by an elution method of the ferrite core material: (MnO)x(MgO)y(Fe2O3)z??(1) wherein x=35 to 45 mol %, y=5 to 15 mol %, z=40 to 60 mol %, and x+y+z=100 mol %.

Abstract: An input processing circuit decodes a digital video signal selected by an input signal selector. Decryption circuits each decrypt the encryption of a video signal output from the input processing circuit, and generate an authentication key of the encryption. A video signal selector selects and outputs one of the video signals output from the decryption circuits, to a monitor. The decryption circuits each include a pseudo-signal generation circuit which extracts information from the video signal, and based on the extracted information, generates a pseudo-video signal.

Abstract: It is an object of the present invention to provide a ferrite carrier core material and a ferrite carrier for an electrophotographic developer, which have an excellent charging property, hardly cause carrier scattering due to cracking and chipping of the core material, and have a prolonged life, and methods for manufacturing these, and an electrophotographic developer using the ferrite carrier. For this object, the ferrite carrier core material and a ferrite carrier for an electrophotographic developer, wherein (1) the ferrite composition contains 0.5 to 2.5% by weight of Sr, and the presence amount of Sr—Fe oxides satisfies a specific conditional expression, (2) the distribution in the number of the shape factor SF-2 is in a specific range, (3) the BET specific surface area is 0.15 to 0.30 m2/g, (4) the average particle diameter D50 is 20 to 35 ?m, and (5) the magnetization is 50 to 65 Am2/kg.

Abstract: There are provided a ferrite carrier core material for an electrophotographic developer, which contain 10 to 30% by weight of Mn, 1.0 to 3.0% by weight of Mg, 0.3 to 1.5% by weight of Ti and 40 to 60% by weight of Fe, a ferrite carrier for an electrophotographic developer obtained by coating the ferrite core material, and an electrophotographic developer using the ferrite carrier.

Abstract: A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.

Abstract: An input processing circuit decodes a digital video signal selected by an input signal selector. Decryption circuits each decrypt the encryption of a video signal output from the input processing circuit, and generate an authentication key of the encryption. A video signal selector selects and outputs one of the video signals output from the decryption circuits, to a monitor. The decryption circuits each include a pseudo-signal generation circuit which extracts information from the video signal, and based on the extracted information, generates a pseudo-video signal.

Abstract: A comparison period detecting unit (11) defines, as a comparison period, a period between a rising edge of a first clock signal and a rising edge of a second clock signal, and detects the presence or absence of transition of a data signal during the comparison period. A phase relationship detecting unit (12) detects a phase relationship between the data signal and a reference clock signal, and outputs a result of detection of the phase relationship when the comparison period detecting unit (11) detects transition of the data signal during the comparison period.

Abstract: It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal.

Abstract: There are provided a ferrite carrier core material for an electrophotographic developer, which contain 10 to 30% by weight of Mn, 1.0 to 3.0% by weight of Mg, 0.3 to 1.5% by weight of Ti and 40 to 60% by weight of Fe, a ferrite carrier for an electrophotographic developer obtained by coating the ferrite core material, and an electrophotographic developer using the ferrite carrier.

Abstract: A crossflow fan includes a rotary impeller formed by curved blades 42. Each of the blades 42 has an outer peripheral edge 43 close to the centrifugal side of the impeller and an inner peripheral edge 44 close to the rotation axis side of the impeller. A plurality of cutouts 45 are formed in the outer peripheral edge 43 and spaced apart at predetermined intervals. Dimples 48 for changing a boundary layer from a laminar flow to a turbulent flow are formed in a negative pressure surface 4q of each blade 42 in the vicinity of the outer peripheral edge 43 to prevent the gas flowing around the blade 42 from separating from the blade 42.

Abstract: The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

Abstract: There is provided a ferrite core material for an electrophotographic developer, the ferrite core material having a ferrite particle composition represented by the formula (1) shown below, containing SrO replacing a part of (MnO) and/or (MgO) in the formula (1) shown below, and having a Cl concentration of 0.1 to 100 ppm, as measured by an elution method of the ferrite core material: (MnO)x(MgO)y(Fe2O3)z ??(1) wherein x=35 to 45 mol %, y=5 to 15 mol %, z=40 to 60 mol %, and x+y+z=100 mol %.

Abstract: A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.

Abstract: A core material of a ferrite carrier for an electrophotographic developer, the core material being composed of a ferrite particle containing at least one or more temperature compensation-type dielectric components selected from Mg2TiO4, MgTiO3 and MgTi2O4, a ferrite carrier for an electrophotographic developer, the ferrite carrier being prepared by coating a surface of the carrier core material with a resin, and an electrophotographic developer using the ferrite carrier.

Abstract: An interface circuit including an LSI (10) in a host device (1), and an LSI (20) in a sub device (2), respectively. The LSI (10) generates a first transmission clock signal (TC1) and a first reception clock signal (RC1) separately in accordance with a first reference clock signal (RFC1). The LSI (10) also generates a second reference clock signal (RFC2) for a sub device (2). The reference clock signal (RFC2) is converted into a differential clock signal, and then transmitted to the sub device (2). An LSI (20) of the sub device (2) generates a second transmission clock signal (TC2) and a second reception clock signal (RC2) separately in accordance with a third reference clock signal (RFC3) converted from the differential clock signal.

Abstract: A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits.

Abstract: The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.