Abstract: A porous ferrite core material for an electrophotographic developer, the porous ferrite core material including Mg in a content of 0.3 to 3% by weight, Ti in a content of 0.4 to 3% by weight and Fe in a content of 60 to 70% by weight, and the porous ferrite core material having a pore volume of 0.04 to 0.16 ml/g, a peak pore size of 0.4 to 1.6 ?m, a saturation magnetization of 40 to 80 Am2/kg, a remanent magnetization of less than 7 Am2/kg and a coercive force of less than 43 A/m; a resin-filled ferrite carrier for an electrophotographic developer obtained by filling a resin in the voids of the porous ferrite core material; and an electrophotographic developer using the ferrite carrier.

Abstract: An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

Abstract: A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.

Abstract: An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time.

Abstract: A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.

Abstract: A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.

Abstract: An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

Abstract: An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

Abstract: In a signal receiving circuit there are provided N input detection circuits 2a to 2n for receiving clock signals S1-c to SN-c included in N channels of signals S1 to SN. Each of the input detection circuits 2a to 2n detects the transition of the input signal of the corresponding channel and further confirms that the signal of the corresponding channel is being received after the transition detection to thereby detect the input of the signal of the corresponding channel. The selection circuit 3 selects and outputs the clock signal and the data signal in the signal of the channel of which the input is detected. The selected output signal is successively subjected to input processes through one each of the phase synchronization circuit 4, the serial/parallel conversion circuit 5, etc., which are shared by N channels.

Abstract: A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.

Abstract: A data transmission circuit transmits transmission data to a receiving apparatus. The clock transmission circuit transmits a transmission clock to the receiving apparatus when the transmission data is transmitted by the data transmission circuit. The phase control circuit varies a phase of the transmission clock to a phase different from that of the transmission data after the transmission clock is transmitted from the clock transmission circuit.

Abstract: A phase adjustment circuit for discretely adjusting a phase of a data signal and that of a clock signal, the phase adjustment circuit including: a delay line for delaying the clock signal to produce a delayed clock signal; a phase comparator for comparing the phase of the data signal with that of the delayed clock signal; a delay control section for outputting a delay control signal based on the comparison result from the phase comparator; and a delay control section for outputting a delay control signal based on a frequency of the clock signal. The delay line determines a delay amount of the delayed clock signal with respect to the clock signal based on the control signals.

Abstract: A centrifugal fan has a circular main plate driven and rotated by a motor rotary shaft, a plurality of blades fixed to an outer circumferential portion of the main plate and spaced apart at predetermined intervals in a circumferential direction of the main plate, and a side plate attached to ends of the blades opposite to the main plate. An air inlet port is formed at the center of the side plate. The side plate inclines outward in centrifugal directions from the air inlet port and has an arcuate cross section with a predetermined radius of curvature. A dead water region reducing space is formed between the blades and the side plate. The dead water region reducing space forms a smooth flow between the two surfaces of each blade, bringing about desirable blade performance.

Abstract: Employment of a carrier core material for an electrophotographic developer containing 0.8 to 5% by weight of Mg, 0.1 to 1.5% by weight of Ti, 60 to 70% by weight of Fe and 0.2 to 2.5% by weight of Sr and having an amount of Sr dissolved with a pH4 standard solution of 80 to 1000 ppm, a carrier using the core material and a process for producing them, and an electrophotographic developer using the carrier.

Abstract: A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

Abstract: A comparison period detecting unit (11) defines, as a comparison period, a period between a rising edge of a first clock signal and a rising edge of a second clock signal, and detects the presence or absence of transition of a data signal during the comparison period. A phase relationship detecting unit (12) detects a phase relationship between the data signal and a reference clock signal, and outputs a result of detection of the phase relationship when the comparison period detecting unit (11) detects transition of the data signal during the comparison period.

Abstract: It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal.

Abstract: A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits.

Abstract: It is contemplated to provide irregular shaped ferrite carrier which has a lower resistance, a high specific surface area, a low specific gravity and a longer operational life, and an electrophotographic developer comprising the ferrite carrier which prevents the toner scattering, has a high image density, and is responsive to high-speed and color imaging. The irregular shaped ferrite carrier is characterized in that the carrier particles are irregular shaped, and 40 percent by number or more of the particles have a rock candy sugar shape and/or an oyster shell shape, and that the shape factor (SF-1=R2/S×?/4×100, wherein R is a maximum length and S is a projected area.) is 140 to 250, and the distribution width (?) is 60 or less.