Abstract: A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

Abstract: The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

Abstract: The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

Abstract: The present invention provides a transmission device, a reception device, a test circuit and a test method, which enable internal parts of the circuit to operate at high speed, while performing inputting/outputting to/from a tester at low speed. The test circuit comprises a PLL 111 which divides the frequency of a test clock input from the tester to generate a PLL clock CKp1, a FIFO 113 which stores input data input from the tester on the test clock and outputs the data on the PLL clock CKp1, an encoder 114 which distributes bits of the input data, a driver 115 which transmits the output signal from the encoder 114 to the outside, a PLL 121 which divides the frequency of the test clock to generate a PLL clock CKp2, a decoder 124 which arranges the bits of the signal received by a receiver 123.

Abstract: An air discharge outlet comprises line air discharge outlets (35) and corner air discharge outlets (36). The line air discharge outlets (35) are so formed as to extend, respectively, along four sides of a casing bottom part having four side parts and four corner parts wherein the side and corner parts are formed in contiguous relationship to one another. The corner air discharge outlets (36) are formed, respectively, in the four casing corner parts so that each corner air discharge outlet (36) establishes connection between adjacent ones of the line air discharge outlets (35). And, each line air discharge outlet (35) is provided with a swing vane (38) swingable about a longitudinal shaft (41) of each line air discharge outlet (35). Each corner air discharge outlet (36) is provided with a fixed stationary vane (39).

Abstract: A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.

Abstract: A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly.

Abstract: A synchronization circuit includes a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock, a delay selection circuit for adding a delay to the input signal based on the control signal, and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.

Abstract: First and second transmission lines and are connected to each other in series. A first terminator is connected to the first transmission line in parallel, and is provided externally of a semiconductor device. A second terminator is connected to the second transmission line in parallel, and is provided inside the semiconductor device. The values of the first and second terminator are adjusted so that the combined resistance value of first and second terminator and the second transmission line matches with the impedance of the first transmission line. Impedance matching of the entire transmission line can be achieved with this simple construction, thus, a stable, high quality signal can be transmitted.

Abstract: The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

Abstract: An analog equalizer includes a mixer and an analog delay circuit. The mixer mixes an input signal and a delayed signal output from the analog delay circuit to output a mixed signal. The analog delay circuit delays the mixed signal output from the mixer to output a delayed signal.

Abstract: The present invention aims at providing a phase comparator and a clock recovery circuit suitable for applications that support data signals with high-speed bit rates in the order of one gigabit per second. Phase comparators receive frequency divided signals NHOLDH and NHOLDL generated from a data signal RD/NRD, respectively, and intermittently perform a phase comparison between a signal dDAT and a signal CLK. This increases the timing margin for the phase comparison and makes it possible to perform a phase comparison for high-speed bit rate signals. The provision of phase comparators that serve as clock recovery circuits makes it possible to handle data signals with high-speed bit rates in the order of one gigabit per second.

Abstract: A terminal resistor built in a signal-sending or signal-receiving semiconductor integrated circuit is composed of a parallel circuit of a polysilicon resistor element having excellent frequency characteristic and a P-type MOS transistor. The resistance value of the polysilicon resistor element is set so as to be an approximate value of the characteristic impedance of a transmission line to be connected. The gate voltage of the P-type MOS transistor is controlled by a gate bias voltage adjustment circuit. The resistance value of the P-type MOS transistor is variably adjusted. Variation in the resistance value of the polysilicon resistor element due to dispersion in its manufacturing process is absorbed by variably adjusting the resistance value of the P-type MOS transistor. The combined resistance value of the polysilicon resistor element and the P-type MOS transistor is adjusted with high precision just to the characteristic impedance of the transmission line.

Abstract: A potential generating circuit comprises a capacitor (4); a ferroelectric capacitor (6) connected in series to the capacitor (4); an output terminal (11); a capacitor (10) for grounding the output terminal (11); a switch (9) for connecting a connecting node (5) between the two capacitors (4, 6) to the output terminal (11); and a switch (1) for connecting the connecting node (5) to the ground; wherein during a first period, with the switches (1) and (9) placed in the OFF state, a terminal (3) is provided with a positive potential and a terminal (7) is grounded; wherein during a second period following the first period, the terminal (3) is grounded and the switch (9) is placed in the ON state; wherein during a third period following the second period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is provided with a positive potential; wherein during a fourth period following the third period, the terminal (7) is grounded; and wherein the first through

Abstract: A multi-phase clock transmission circuit includes: a clock generator for generating a clock synchronizing with a reference clock and a control signal responsive to the phase difference between the reference clock and the generated clock; and a delay circuit for generating a multi-phase clock based on the clock and the control signal. The clock generator generates a signal having a frequency equal to an integral multiple of the frequency of the reference clock and outputs the signal as the clock. The delay circuit has a circuit receiving the clock and including a plurality of delay elements in cascade connection each giving a delay according to the control signal to an input signal. Signals output from the plurality of delay elements are used as signals constituting the multi-phase clock.

Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

Abstract: A synchronization circuit comprises a state detection circuit for outputting a control signal according to the temporal relationship between a transition point of an input signal and an edge of a synchronization clock; a delay selection circuit for adding a delay to the input signal on the basis of the control signal; and a latch circuit for synchronizing the signal outputted from the delay selection circuit with the synchronization clock. Therefore, synchronization of the input signal can be carried out without adding latency to the input signal.

Abstract: The clock recovery circuit includes a first oscillator and an edge detector. The first oscillator generates a plurality of clocks having different phases and a predetermined frequency. The edge detector detects two clocks, among the plurality of clocks, between edges of which an input data signal has made a transition. The first oscillator includes a plurality of delay cells connected in a ring, and outputs of the plurality of delay cells are output as the plurality of clocks. Each of the plurality of delay cells selectively delays a first-delay added input data signal or the signal output from the preceding delay cell, and outputs the selected delayed signal. The edge detector controls one delay cell among the plurality of delay cells corresponding to the result of the detection, to delay and output the first-delay added input data signal.

Abstract: A potential generating circuit comprises a capacitor (4); a ferroelectric capacitor (6) connected in series to the capacitor (4); an output terminal (11); a capacitor (10) for grounding the output terminal (11); a switch (9) for connecting a connecting node (5) between the two capacitors (4, 6) to the output terminal (11); and a switch (1) for connecting the connecting node (5) to the ground; wherein during a first period, with the switches (1) and (9) placed in the OFF state, a terminal (3) is provided with a positive potential and a terminal (7) is grounded; wherein during a second period following the first period, the terminal (3) is grounded and the switch (9) is placed in the ON state; wherein during a third period following the second period, the switch (9) is placed in the OFF state, the switch (1) is placed in the ON state, and the terminal (7) is provided with a positive potential; wherein during a fourth period following the third period, the terminal (7) is grounded; and wherein the first through

Abstract: A semiconductor device includes: a transmitting section; and a receiving section, wherein the transmitting section and the receiving section are connected to each other through a bus, the transmitting section includes an encoding section for encoding data including a plurality of bits to produce bit-position information which indicates a position of at least one bit selected from the plurality of bits included in the data, and an output section for outputting the bit-position information onto the bus, and the receiving section includes an input section for receiving the bit-position information from the bus, and a decoding section for decoding the bit-position information to produce the data.