Patents by Inventor Toshiaki Ono

Toshiaki Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200047273
    Abstract: The purpose of the present invention is to reduce the amount of sputtering in a welding method wherein a welding wire feed rate is alternately switched between a forward feed period and a reverse feed period. Provided is an arc welding control method that switches a feed rate Fw for welding wire alternately between a forward feed period and a reverse feed period, repeats a short period and an arc period, and electrifies with a welding current Iw switched to a small current value in the latter half of the arc period, wherein a basic voltage setting value is set according to an average feed rate setting value, the error amplitude value for a voltage setting value and the basic voltage setting value is calculated, and the timing (current reduction time Td) for switching the welding current Iw to the small current value is varied on the basis of the average feed rate setting value and the error amplitude value.
    Type: Application
    Filed: July 6, 2017
    Publication date: February 13, 2020
    Applicant: DAIHEN CORPORATION
    Inventors: Kohei ONO, Toshiaki NAKAMATA
  • Publication number: 20200051817
    Abstract: A manufacturing method of an epitaxial silicon wafer includes: an epitaxial-film formation step for forming an epitaxial film made of silicon on a surface of a silicon wafer in a trichlorosilane gas atmosphere; and a nitrogen-concentration setting step for setting the nitrogen concentration of the surface of the epitaxial film through inward diffusion from a nitride film on the epitaxial film, the nitride film being formed by subjecting the silicon wafer provided with the epitaxial film through the epitaxial-film formation step to a heat treatment in a nitrogen atmosphere.
    Type: Application
    Filed: September 12, 2017
    Publication date: February 13, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Kazuya KODANI, Toshiaki ONO, Kazuhisa TORIGOE
  • Publication number: 20200020817
    Abstract: A method of manufacturing an epitaxial silicon wafer that includes growing a silicon single crystal ingot doped with a boron concentration of 2.7×1017 atoms/cm3 or more and 1.3×1019 atoms/cm3 or less by the CZ method; producing a silicon substrate by processing the silicon single crystal ingot; and forming an epitaxial layer on a surface of the silicon substrate. During growing of the silicon single crystal ingot, the pull-up conditions of the silicon single crystal ingot are controlled so that the boron concentration Y (atoms/cm3) and an initial oxygen concentration X (×1017 atoms/cm3) satisfy the expression X??4.3×10?19Y+16.3.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Kazuhisa TORIGOE, Toshiaki ONO
  • Publication number: 20190358724
    Abstract: In an arc start control method for forward and reverse feed arc welding in which forward and reverse feed control of alternately switching a feed speed Fw of a welding wire between a forward feed period and a reverse feed period is performed to generate a short circuit period and an arc period to perform welding, at arc start, a pulse period Tp during which a pulse current is energized for a plurality of number of times is provided, and thereafter forward and reverse feed control is started from forward feed period of the welding wire. During the pulse period Tp, a forward feed speed Fp of the welding wire is set so that the arc period is continuous. In addition, the forward feed speed Fp is changed based on a time length of pulse period Tp and/or a value of a welding voltage Vw during pulse period Tp.
    Type: Application
    Filed: December 7, 2017
    Publication date: November 28, 2019
    Applicant: DAIHEN CORPORATION
    Inventors: Kohei ONO, Toshiaki NAKAMATA
  • Patent number: 10488751
    Abstract: Provided are a pellicle for extreme ultraviolet light lithography, a production method thereof, and an exposure method. A pellicle according to the present invention includes a first frame having a pellicle film located thereon; a second frame including a thick portion including a first surface carrying a surface of the first frame opposite to a surface on which the pellicle film is located, and also including a second surface connected with the first surface and carrying a side surface of the first frame, the second frame enclosing the pellicle film and the first frame; a through-hole provided in the thick portion of the second frame; and a filter located on an outer side surface of the second frame and covering the through-hole, the outer side surface crossing the surface of the first frame on which the pellicle film is located.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: November 26, 2019
    Assignee: MITSUI CHEMICALS, INC.
    Inventors: Kazuo Kohmura, Daiki Taneichi, Yosuke Ono, Hisako Ishikawa, Tsuneaki Biyajima, Atsushi Okubo, Yasuyuki Sato, Toshiaki Hirota
  • Publication number: 20190352796
    Abstract: Provided is a method of producing a high resistance n-type silicon single crystal ingot with small tolerance margin on resistivity in the crystal growth direction, which is suitably used in a power device. In the method of producing a silicon single crystal ingot using Sb or As as an n-type dopant, while a silicon single crystal ingot is pulled up, the amount of the n-type dopant being evaporated from a silicon melt per unit solidification ratio is kept within a target evaporation amount range per unit solidification ratio by controlling one or more pulling condition values including at least one of the pressure in a chamber, the flow volume of Ar gas, and a gap between a guide portion and the silicon melt.
    Type: Application
    Filed: January 11, 2018
    Publication date: November 21, 2019
    Applicant: SUMCO CORPORATION
    Inventors: Masataka HOURAI, Wataru SUGIMURA, Toshiaki ONO, Toshiyuki FUJIWARA
  • Publication number: 20190337080
    Abstract: An arc welding control method for controlling welding in which a material of a welding wire is aluminum or an aluminum alloy, and a feed speed Fw of the welding wire is alternately switched between a forward feed period and a reverse feed period to repeat a short circuit period and an arc period, a welding current Iw is controlled so that an average value of maximum values of the welding current Iw during the short circuit period is 150 A or less. A reverse feed peak value Wrp during the reverse feed period is set so that an average value of time lengths of the short circuit period is 7 ms or less. Accordingly, the current value can be reduced when the short circuit is released and the lengthening in the short circuit period can be prevented, so that the spatter generation amount can be reduced.
    Type: Application
    Filed: January 12, 2018
    Publication date: November 7, 2019
    Applicant: DAIHEN CORPORATION
    Inventors: Kohei ONO, Toshiaki NAKAMATA
  • Publication number: 20190258340
    Abstract: A display device according to the present invention includes a touch panel, a dielectric sheet, a frame, and a display panel. The touch panel has a touch sensor portion in the middle and a first electrode in an inner peripheral portion. Further, the dielectric sheet is closely adhered the back surface of the touch panel in its front surface. The frame has an opening in the central portion thereof and a second electrode in a marginal portion that is closely adhered the back surface of the dielectric sheet. The display panel has a display surface to display a screen image and the display surface is closely adhered the back surface of the dielectric sheet in the opening of the frame. The first electrode and the second electrode constitute a pressure-sensitive sensor that has a function to detect a pressing force when an operation element touches the front surface of the touch panel.
    Type: Application
    Filed: October 12, 2017
    Publication date: August 22, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masafumi AGARI, Tae ORITA, Takeshi ONO, Toshiaki FUJINO, Kozo ISHIDA, Seiichiro MORI
  • Publication number: 20190251921
    Abstract: A shift register circuit that controls back gate voltage of a transistor with a simple configuration and at a low cost, and a display panel. In the shift register circuit, shift registers include: an output circuit, a charge and discharge circuit, a first power supply terminal, and at least one back gate voltage generation circuit. The output circuit or the charge and discharge circuit includes at least one transistor. The back gate voltage generation circuit includes a back gate node. The back gate node is connected to the back gate electrode of the transistor. The back gate voltage generation circuit changes a voltage of the back gate node according to a voltage of a gate electrode of the transistor. The back gate voltage generation circuit is supplied with a drive voltage from the first power supply terminal.
    Type: Application
    Filed: May 25, 2017
    Publication date: August 15, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takeshi ONO, Masafumi AGARI, Toshiaki FUJINO, Shinji KAWABUCHI
  • Patent number: 10374166
    Abstract: A novel polycyclic aromatic compound in which plural aromatic rings are linked via boron atoms, oxygen atoms and the like is provided, and therefore, the range of selection of the material for organic electroluminescent elements can be widened. Also, an excellent organic electroluminescent element is provided by using the novel polycyclic aromatic compound as a material for an organic electroluminescent element.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: August 6, 2019
    Assignees: KWANSEI GAKUIN EDUCATIONAL FOUNDATION, JNC CORPORATION
    Inventors: Takuji Hatakeyama, Soichiro Nakatsuka, Kiichi Nakajima, Hiroki Hirai, Yohei Ono, Kazushi Shiren, Jingping Ni, Takeshi Matsushita, Toshiaki Ikuta
  • Publication number: 20190232415
    Abstract: A method is provided for controlling arc welding including forward and reverse feeding periods alternately switched. By the method, a set of a short circuit period and an arc period is repeated, and the arc welding is controlled such that the reverse feeding period shifts to the forward feeding period when an arc occurs during the reverse feeding period, and that the forward feeding period shifts to the reverse feeding period when a short circuit occurs between the welding wire and the object during the forward feeding period. The reverse feeding period includes a reverse feeding deceleration period having a time length that is adjusted in accordance with the time length of the short circuit period.
    Type: Application
    Filed: January 18, 2019
    Publication date: August 1, 2019
    Inventors: Kohei ONO, Toshiaki NAKAMATA, Kento TAKADA
  • Publication number: 20190214575
    Abstract: Provided is an organic electroluminescent element which has improved driving voltage and improved current efficiency. An organic electroluminescent element having the above-mentioned improved characteristics is provided by using, as a material for organic electroluminescent elements, a polycyclic aromatic compound in which a nitrogen atom and another heteroatom or a metal atom (X) are adjacent to each other in a non-aromatic ring.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Applicants: JNC Corporation, Kyoto University
    Inventors: Yohei ONO, Kazushi SHIREN, Toshiaki IKUTA, Jingping NI, Takeshi MATSUSHITA, Takuji HATAKEYAMA, Masaharu NAKAMURA, Shiguma HASHIMOTO
  • Publication number: 20190037160
    Abstract: At least one solid-state image pickup element includes a plurality of pixels that are arranged in a two-dimensional manner. Each of the plurality of pixels includes a plurality of photoelectric conversion units each including a pixel electrode, a photoelectric conversion layer disposed on the pixel electrode, and a counter electrode disposed such that the photoelectric conversion layer is sandwiched between the pixel electrode and the counter electrode. In one or more embodiments, each of the plurality of pixels also includes a microlens disposed on the plurality of photoelectric conversion units.
    Type: Application
    Filed: October 1, 2018
    Publication date: January 31, 2019
    Inventors: Toshiaki Ono, Masatsugu Itahashi, Naoki Inatani, Yu Maehashi, Hidekazu Takahashi
  • Patent number: 10192754
    Abstract: A method for producing an epitaxial silicon wafer, including a preliminary thermal treatment step of subjecting a silicon wafer to thermal treatment for increasing a density of oxygen precipitates, the silicon wafer being one that has an oxygen concentration in a range of 9×1017 atoms/cm3 to 16×1017 atoms/cm3, contains no dislocation cluster and no COP, and contains an oxygen precipitation suppression region, and an epitaxial layer forming step of forming an epitaxial layer on a surface of the silicon wafer after the preliminary thermal treatment step. The production method further includes a thermal treatment condition determining step of determining a thermal treatment condition in the preliminary thermal treatment step, based on a ratio of the oxygen precipitation suppression region of the silicon wafer before the preliminary thermal treatment step is carried out.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: January 29, 2019
    Assignee: SUMCO CORPORATION
    Inventors: Jun Fujise, Toshiaki Ono
  • Publication number: 20180337306
    Abstract: A manufacturing method for a group III nitride semiconductor substrate is provided with a first step of forming a second group III nitride semiconductor layer on a substrate; a second step of forming a protective layer on the second group III nitride semiconductor layer; a third step of selectively forming pits on dislocation portions of the second group III nitride semiconductor layer by gas-phase etching applied to the protective layer and the second group III nitride semiconductor layer; and a fourth step of forming a third group III nitride semiconductor layer on the second group III nitride semiconductor layer and/or the remaining protective layer so as to allow the pits to remain.
    Type: Application
    Filed: November 1, 2016
    Publication date: November 22, 2018
    Applicant: SUMCO CORPORATION
    Inventors: Koji MATSUMOTO, Toshiaki ONO, Hiroshi AMANO, Yoshio HONDA
  • Patent number: 10136091
    Abstract: At least one solid-state image pickup element includes a plurality of pixels that are arranged in a two-dimensional manner. Each of the plurality of pixels includes a plurality of photoelectric conversion units each including a pixel electrode, a photoelectric conversion layer disposed on the pixel electrode, and a counter electrode disposed such that the photoelectric conversion layer is sandwiched between the pixel electrode and the counter electrode. In one or more embodiments, each of the plurality of pixels also includes a microlens disposed on the plurality of photoelectric conversion units.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 20, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiaki Ono, Masatsugu Itahashi, Naoki Inatani, Yu Maehashi, Hidekazu Takahashi
  • Patent number: 10110797
    Abstract: Provided is an imaging device that includes a pixel unit in which each of a plurality of pixels includes m photoelectric conversion units and each of at least a part of the plurality of pixels outputs a first signal based on signal charges of n photoelectric conversion unit or units, where n is less than m; an adder unit configured to add a plurality of first signals output from a plurality of pixels different from each other; a determination unit configured to compare each of the plurality of first signals and a predetermined threshold to determine whether or not the plurality of first signals added by the adder unit include a signal larger than a predetermined threshold; and an output unit configured to output a determination result and the added signal.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: October 23, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Toshiaki Ono
  • Publication number: 20180294307
    Abstract: Each of a plurality of pixels arranged in two dimensions includes a photoelectric conversion unit including a pixel electrode, a photoelectric conversion layer provided above the pixel electrode, and a counter electrode provided so as to sandwich the photoelectric conversion layer between the counter electrode and the pixel electrode, and a microlens arranged above the photoelectric conversion unit. The plurality of pixels includes a first pixel and a plurality of second pixels. At least either the pixel electrodes of the plurality of second pixels are smaller than the pixel electrode of the first pixel or the counter electrodes of the plurality of second pixels are smaller than the counter electrode of the first pixel, and a configuration between the counter electrode and the microlens of the first pixel is the same as a configuration between the counter electrode and the microlens of each of the plurality of second pixels.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: Masatsugu Itahashi, Toshiaki Ono, Hidekazu Takahashi, Naoki Inatani, Yu Maehashi
  • Patent number: 10084980
    Abstract: A solid-state image sensor includes an image sensing unit in which a plurality of pixels are arrayed, a plurality of readout units configured to read out signals from the image sensing unit, a detector configured to detect an occurrence of a latch-up in each of the plurality of readout units, and a controller configured to control power supply to the plurality of readout units. The plurality of readout units are configured to read out signals from a same pixel in the image sensing unit. The controller is configured to shut off power supply to at least part of a readout unit in which the occurrence of the latch-up has been detected out of the plurality of readout units and thereafter supply power to the at least part.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: September 25, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Moriyama, Kazuaki Tashiro, Tatsuhito Goden, Toshiaki Ono
  • Publication number: 20180204960
    Abstract: An epitaxial silicon wafer is provided with a boron-doped silicon substrate and an epitaxial layer formed on a surface of the silicon substrate, wherein the boron concentration in the silicon substrate is 2.7×1017 atoms/cm3 or more and 1.3×1019 atoms/cm3 or less, and an initial oxygen concentration in the silicon substrate is 11×1017 atoms/cm3 or less. When an oxygen precipitate evaluation heat treatment, such as a heat treatment at 700° C. for 3 hours and a heat treatment at 1,000° C. for 16 hours is executed on the epitaxial silicon wafer, the density of oxygen precipitate in the silicon substrate is 1×1010/cm3 or less.
    Type: Application
    Filed: July 6, 2016
    Publication date: July 19, 2018
    Applicant: SUMCO CORPORATION
    Inventors: Kazuhisa TORIGOE, Toshiaki ONO