Patents by Inventor Toshiaki Ono

Toshiaki Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240385855
    Abstract: Mechanisms are provided for identifying execution paths in computer application logic. A control flow graph is generated for the computer application logic based on source code and an execution log. Paths of the control flow graph are identified that have operators matching operators having execution counts in the execution log. An operator list for each path is generated specifying operators in the path. An operator count expression is generated for each operator in the operator list for each path. For each path, a relationship is generated between the path's operator count expression and actual execution count information for operators in the path's operator list. An execution possibility value is estimated for each path based on the relationships for each path, and a second set of paths having execution possibility values indicating they are possible execution paths of the computer application logic is output.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 21, 2024
    Inventors: Toshiaki Yasue, Kohichi Ono, Nobuhiro Hosokawa, Hiroaki Nakamura
  • Patent number: 12142645
    Abstract: A silicon wafer having a layer of oxygen precipitates and method of manufacturing thereof wherein the wafer exhibiting robustness characterized as having a ratio of a first average density from a first treatment that to a second average density from a second treatment is between 0.74 to 1.02, wherein the first treatment includes heating the wafer or a portion of the wafer at about 1150° C. for about 2 minutes and then between about 950 to 1000° C. for about 16 hours, and the second treatment includes heating the wafer or a portion of the wafer at about 780° C. for about 3 hours and then between about 950 to 1000° C. for about 16 hours. The wafer exhibits heretofore unattainable uniformity wherein a ratio of an oxygen precipitate density determined from any one cubic centimeter in the BMD layer of the wafer to another oxygen precipitate density from any other one cubic centimeter in the BMD layer of the wafer is in a range of 0.77 to 1.30.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: November 12, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Kazuhisa Torigoe, Toshiaki Ono, Shunya Kawaguchi
  • Publication number: 20240339474
    Abstract: The present disclosure relates to a light detection device and an electronic apparatus that are configured to be able to increase the circuit occupancy area within a substrate.
    Type: Application
    Filed: March 8, 2022
    Publication date: October 10, 2024
    Inventors: TAKAHIRO MAYUMI, TOSHIAKI ONO
  • Publication number: 20240276120
    Abstract: To improve the image quality in a solid-state imaging element that performs CDS processing. The solid-state imaging element includes an amplitude detection unit and a black spot prevention unit. The amplitude detection unit detects whether an output voltage that is a voltage of a vertical signal line for transmitting either a reset level at which a pixel is initialized or a signal level corresponding to an amount of light exceeds a predetermined determination threshold. The black spot prevention unit controls, when the output voltage exceeds the determination threshold, a first digital signal obtained by converting the reset level and a second digital signal obtained by converting the signal level to different values.
    Type: Application
    Filed: December 28, 2021
    Publication date: August 15, 2024
    Inventors: Mamoru Sato, Masaki Sakakibara, Toshiaki Ono
  • Publication number: 20240271920
    Abstract: The present strain gauge is a strain gauge installed on a Roberval-type strain generator, and includes a substrate having flexibility; and a resistor formed of a film that contains Cr, CrN, and Cr2N over the substrate, wherein a film thickness of the resistor is greater than or equal to 6 nm and less than or equal to 100 nm.
    Type: Application
    Filed: March 24, 2022
    Publication date: August 15, 2024
    Inventors: Aya ONO, Yosuke OGASA, Toshiaki ASAKAWA, Akiyo YUGUCHI, Atsushi KITAMURA
  • Publication number: 20240204028
    Abstract: An imaging device of an embodiment has a first substrate, a second substrate, a wire, and a trench. The first substrate has a pixel having a photodiode and a floating diffusion that holds a charge converted by the photodiode. The second substrate has a pixel circuit that reads a pixel signal based on the charge held in the floating diffusion in the pixel, and is stacked on the first substrate. The wire penetrates the first substrate and the second substrate in a stacking direction, and electrically connects the floating diffusion in the first substrate to an amplification transistor in the pixel circuit of the second substrate. The trench is formed at least in the second substrate, runs in parallel with the wire, and has a depth equal to or greater than the thickness of a semiconductor layer in the second substrate.
    Type: Application
    Filed: December 28, 2023
    Publication date: June 20, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takeyoshi KOMOTO, Masahiko NAKAMIZO, Toshiaki ONO, Tomonori YAMASHITA
  • Patent number: 12004344
    Abstract: A method of reducing warp imparted to a silicon wafer having a (110) plane orientation and a <111> notch orientation by anisotropic film stress of a multilayer film that is to be formed on a surface of the silicon wafer, that includes forming the multilayer film on a surface of the silicon wafer in an orientation so that a direction in which the warp of the wafer will be greatest coincides with a direction in which Young's modulus of a crystal orientation of the silicon wafer is greatest. Also, a method of reducing warp imparted to a silicon wafer having a (111) plane orientation by isotropic film stress of a multilayer film to be formed on a surface of the silicon wafer, that includes, prior to forming the multilayer film, causing the silicon wafer to have an oxygen concentration of 8.0×1017 atoms/cm3 or more (ASTM F-121, 1979).
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: June 4, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Toshiaki Ono, Bong-Gyun Ko
  • Patent number: 12002823
    Abstract: A solid-state image sensor includes a plurality of imaging device blocks each including P×Q imaging devices. In an imaging device block, first charge movement controlling electrodes are provided between the imaging devices, and second charge movement controlling electrodes are provided between the imaging device blocks. In the imaging device block, P imaging devices are arrayed along a first direction, and Q imaging devices are arrayed along a second direction. Charge accumulated in a photoelectric conversion layer of the (P?1)th imaging device from the first imaging device along the first direction is transferred to the photoelectric conversion layer of the Pth imaging device and read out together with charge accumulated in the photoelectric conversion layers of the Q Pth imaging devices, under the control of the first charge movement controlling electrodes.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: June 4, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Toshiaki Ono
  • Patent number: 11990486
    Abstract: A solid-state imaging device according to an embodiment of the present disclosure includes a stacked photoelectric converter for each of pixels. The stacked photoelectric converter has a plurality of photoelectric conversion elements stacked therein. The plurality of photoelectric conversion elements each has different wavelength selectivity. This solid-state imaging device further includes a plurality of data output lines from which pixel signals based on electric charges outputted from the photoelectric conversion elements are outputted. A plurality of data output lines is provided for each predetermined unit pixel column. The plurality of the data output lines is equal in number to an integer multiple of the photoelectric conversion elements stacked in the stacked photoelectric converter.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 21, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Toshiaki Ono
  • Publication number: 20240071756
    Abstract: A method for manufacturing a group III nitride semiconductor substrate, that includes: growing a first AlN buffer layer on an Si substrate at a first growth temperature; growing a second AlN buffer layer on the first AlN buffer layer at a second growth temperature higher than the first growth temperature; and growing a group III nitride semiconductor layer on the second AlN buffer layer, wherein an Al raw material and an N raw material are alternately repeatedly fed in the growing the first AlN buffer layer.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 29, 2024
    Applicant: SUMCO CORPORATION
    Inventors: Koji MATSUMOTO, Toshiaki ONO, Hiroshi AMANO, Yoshio HONDA
  • Patent number: 11901391
    Abstract: An imaging device of an embodiment has a first substrate, a second substrate, a wire, and a trench. The first substrate has a pixel having a photodiode and a floating diffusion that holds a charge converted by the photodiode. The second substrate has a pixel circuit that reads a pixel signal based on the charge held in the floating diffusion in the pixel, and is stacked on the first substrate. The wire penetrates the first substrate and the second substrate in a stacking direction, and electrically connects the floating diffusion in the first substrate to an amplification transistor in the pixel circuit of the second substrate. The trench is formed at least in the second substrate, runs in parallel with the wire, and has a depth equal to or greater than the thickness of a semiconductor layer in the second substrate.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: February 13, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takeyoshi Komoto, Masahiko Nakamizo, Toshiaki Ono, Tomonori Yamashita
  • Publication number: 20240038788
    Abstract: A solid-state imaging device according to an embodiment of the present disclosure includes a stacked photoelectric converter for each of pixels. The stacked photoelectric converter has a plurality of photoelectric conversion elements stacked therein. The plurality of photoelectric conversion elements each has different wavelength selectivity. This solid-state imaging device further includes a plurality of data output lines from which pixel signals based on electric charges outputted from the photoelectric conversion elements are outputted. A plurality of data output lines is provided for each predetermined unit pixel column. The plurality of the data output lines is equal in number to an integer multiple of the photoelectric conversion elements stacked in the stacked photoelectric converter.
    Type: Application
    Filed: October 6, 2023
    Publication date: February 1, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Toshiaki ONO
  • Patent number: 11885038
    Abstract: A convection pattern estimation method of a silicon melt includes: applying a horizontal magnetic field of 0.2 tesla or more to a silicon melt in a rotating quartz crucible with use of a pair of magnetic bodies disposed across the quartz crucible; before a seed crystal is dipped into the silicon melt to which the horizontal magnetic field is applied; measuring temperatures at a first and second measurement points positioned on a first imaginary line that passes through a center of a surface of the silicon melt and is not in parallel with a central magnetic field line of the horizontal magnetic field as viewed vertically from above; and estimating a direction of a convection flow in a plane in the silicon melt orthogonal to the direction in which the horizontal magnetic field is applied on a basis of the measured temperatures of the first and second measurement points.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: January 30, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Wataru Sugimura, Ryusuke Yokoyama, Toshiyuki Fujiwara, Toshiaki Ono
  • Patent number: 11888036
    Abstract: A manufacturing method of an epitaxial silicon wafer includes forming an epitaxial film made of silicon on a surface of a silicon wafer in a trichlorosilane gas atmosphere; and setting the nitrogen concentration of the surface of the epitaxial film through inward diffusion from a nitride film on the epitaxial film, the nitride film being formed by subjecting the silicon wafer provided with the epitaxial film to heat treatment in a nitrogen atmosphere.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: January 30, 2024
    Assignee: SUMCO CORPORATION
    Inventors: Kazuya Kodani, Toshiaki Ono, Kazuhisa Torigoe
  • Publication number: 20240022839
    Abstract: The present technology relates to an imaging device and an imaging method capable of improving image quality of an image captured by the imaging device. The present technology includes: a photoelectric conversion section that performs photoelectric conversion; a first capacitor that holds a first signal from the photoelectric conversion section; a second capacitor that holds a second signal from the photoelectric conversion section; a first reading section that reads the first signal held in the first capacitor; a second reading section that reads the second signal held in the second capacitor; a differential circuit in which the first signal from the first reading section is input at one end and the second signal from the second reading section is input at another end; and an initialization section that initializes the differential circuit. The present technology can be applied to, for example, an imaging device.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 18, 2024
    Inventor: TOSHIAKI ONO
  • Patent number: 11855108
    Abstract: A solid-state imaging element which detects visible light and ultraviolet light in one pixel provides improved resolution. First and second photoelectric conversion elements each perform photoelectric conversion of incident light. A first accumulation part accumulates electric charges that are photoelectrically converted by the first photoelectric conversion element second accumulation part is disposed on one face of a substrate and accumulates electric charges that are photoelectrically converted by the second photoelectric conversion element. A connection part is connected to the second accumulation part and transfers the electric charges accumulated in the second accumulation part to another face of the substrate.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: December 26, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Satoko Iida, Yoshiaki Kitano, Kengo Nagata, Toshiaki Ono, Tomohiko Asatsuma
  • Publication number: 20230412945
    Abstract: The present technology relates to an image pickup apparatus capable of improving image quality of an image captured by the image pickup apparatus. Included are a photoelectric conversion unit that performs photoelectric conversion, a first capacitor and a second capacitor that hold a signal from the photoelectric conversion unit, and an initialization switch that initializes the second capacitor, in which one end of the first capacitor, one end of the second capacitor, and an amplification unit that amplifies a signal from the photoelectric conversion unit are connected, another end of the second capacitor and one end of the initialization switch are connected, and another end of the first capacitor and another end of the initialization switch are connected to a voltage source. The present technology can be applied to, for example, an image pickup apparatus.
    Type: Application
    Filed: October 29, 2021
    Publication date: December 21, 2023
    Inventor: TOSHIAKI ONO
  • Publication number: 20230412943
    Abstract: The present technology relates to an imaging device and an imaging method capable of improving image quality of an image captured by the imaging device. The present technology includes: a photoelectric conversion section that performs photoelectric conversion; a first capacitor that holds a first signal from the photoelectric conversion section; a second capacitor that holds a second signal from the photoelectric conversion section; a first reading section that reads the first signal held in the first capacitor; a second reading section that reads the second signal held in the second capacitor; a differential circuit in which the first signal from the first reading section is input at one end and the second signal from the second reading section is input at another end; and an initialization section that initializes the differential circuit. The present technology can be applied to, for example, an imaging device.
    Type: Application
    Filed: October 26, 2021
    Publication date: December 21, 2023
    Inventor: TOSHIAKI ONO
  • Publication number: 20230307505
    Abstract: A silicon wafer having a layer of oxygen precipitates and method of manufacturing thereof wherein the wafer exhibiting robustness characterized as having a ratio of a first average density from a first treatment that to a second average density from a second treatment is between 0.74 to 1.02, wherein the first treatment includes heating the wafer or a portion of the wafer at about 1150° C. for about 2 minutes and then between about 950 to 1000° C. for about 16 hours, and the second treatment includes heating the wafer or a portion of the wafer at about 780° C. for about 3 hours and then between about 950 to 1000° C. for about 16 hours. The wafer exhibits heretofore unattainable uniformity wherein a ratio of an oxygen precipitate density determined from any one cubic centimeter in the BMD layer of the wafer to another oxygen precipitate density from any other one cubic centimeter in the BMD layer of the wafer is in a range of 0.77 to 1.30.
    Type: Application
    Filed: June 5, 2023
    Publication date: September 28, 2023
    Applicant: SUMCO CORPORATION
    Inventors: Kazuhisa TORIGOE, Toshiaki ONO, Shunya KAWAGUCHI
  • Publication number: 20230303026
    Abstract: Provided are a forming method of forming, with high efficiency, a tear line groove even with a layout of unsuitable for processing for drawing a locus in a unicursal manner, and an instrument panel formed by the forming method. The forming method is a method of forming a tear line groove in an airbag deployment portion, the tear line groove including: an airbag deployment portion forming step of applying, as one die of two dies constituting a cavity into which a molten resin is injected to form the airbag deployment portion, a die having a ridge protruding inwardly in the cavity to form a part of the tear line groove; and a post-processing step of processing the remaining tear line groove, which were not formed in the airbag deployment portion forming step.
    Type: Application
    Filed: February 23, 2023
    Publication date: September 28, 2023
    Inventors: Toshihisa KAGA, Toshiaki ONO, Takaaki NAGATA, Shoichiro NEGISHI