Patents by Inventor Toshiaki Ono

Toshiaki Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210132997
    Abstract: A process control unit (41) causes a plurality of control-target processes to operate in a memory area of a size equal to or smaller than a limiting value x. When a stopping process is detected, a resource allocation unit (43) allocates a size of a usable memory area for each of the control-target processes as a relaxed limiting value. When the stopping process is detected, the process control unit (41) causes each of the control-target processes to perform fallback operation in a memory area of a size equal to or smaller than the relaxed limiting value allocated to the process by the resource allocation unit (43).
    Type: Application
    Filed: February 28, 2018
    Publication date: May 6, 2021
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuya ONO, Hirotaka MOTAI, Masahiro DEGUCHI, Shinichi OCHIAI, Hiroki KONAKA, Shunsuke NISHIO, Toshiaki TOMISAWA
  • Patent number: 10910328
    Abstract: Provided is a silicon wafer manufacturing method capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer manufacturing method according to the present invention is provided with calculating a target thickness of the silicon wafer required for ensuring a warpage reduction amount of a silicon wafer warped during a device process from a relationship between an amount of warpage of a silicon wafer and a thickness thereof occurring due to application of the same film stress to a plurality of silicon wafers having mutually different thicknesses; and processing a silicon single crystal ingot to thereby manufacture silicon wafers having the target thickness.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: February 2, 2021
    Assignee: SUMCO CORPORATION
    Inventors: Bong-Gyun Ko, Toshiaki Ono
  • Publication number: 20200399780
    Abstract: A convection pattern estimation method of a silicon melt includes: applying a horizontal magnetic field of 0.2 tesla or more to a silicon melt in a rotating quartz crucible with use of a pair of magnetic bodies disposed across the quartz crucible; before a seed crystal is dipped into the silicon melt to which the horizontal magnetic field is applied; measuring temperatures at a first and second measurement points positioned on a first imaginary line that passes through a center of a surface of the silicon melt and is not in parallel with a central magnetic field line of the horizontal magnetic field as viewed vertically from above; and estimating a direction of a convection flow in a plane in the silicon melt orthogonal to the direction in which the horizontal magnetic field is applied on a basis of the measured temperatures of the first and second measurement points.
    Type: Application
    Filed: February 27, 2019
    Publication date: December 24, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Wataru SUGIMURA, Ryusuke YOKOYAMA, Toshiyuki FUJIWARA, Toshiaki ONO
  • Patent number: 10861990
    Abstract: A method of manufacturing an epitaxial silicon wafer that includes growing a silicon single crystal ingot doped with a boron concentration of 2.7×1017 atoms/cm3 or more and 1.3×1019 atoms/cm3 or less by the CZ method; producing a silicon substrate by processing the silicon single crystal ingot; and forming an epitaxial layer on a surface of the silicon substrate. During growing of the silicon single crystal ingot, the pull-up conditions of the silicon single crystal ingot are controlled so that the boron concentration Y (atoms/cm3) and an initial oxygen concentration X (×1017 atoms/cm3) satisfy the expression X??4.3×10?19Y+16.3.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: December 8, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Kazuhisa Torigoe, Toshiaki Ono
  • Patent number: 10777704
    Abstract: A manufacturing method for a group III nitride semiconductor substrate is provided with a first step of forming a second group III nitride semiconductor layer on a substrate; a second step of forming a protective layer on the second group III nitride semiconductor layer; a third step of selectively forming pits on dislocation portions of the second group III nitride semiconductor layer by gas-phase etching applied to the protective layer and the second group III nitride semiconductor layer; and a fourth step of forming a third group III nitride semiconductor layer on the second group III nitride semiconductor layer and/or the remaining protective layer so as to allow the pits to remain.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 15, 2020
    Assignee: SUMCO CORPORATION
    Inventors: Koji Matsumoto, Toshiaki Ono, Hiroshi Amano, Yoshio Honda
  • Publication number: 20200260026
    Abstract: Provided is a solid-state imaging element configured to automatically extend dynamic range for each unit pixel. A solid-state imaging element includes, for a unit pixel, a first photoelectric conversion element, a first accumulation portion that accumulates electric charge obtained by photoelectric conversion by the first photoelectric conversion element, and a first film that is electrically connected to the first accumulation portion and has an optical characteristic changing according to applied voltage. Furthermore, the unit pixel of the solid-state imaging element can further include a first transfer transistor that transfers electric charge obtained by photoelectric conversion by the photoelectric conversion element to the first accumulation portion, an amplification transistor that is electrically connected to the first accumulation portion, and a selection transistor that is electrically connected to the amplification transistor.
    Type: Application
    Filed: October 12, 2018
    Publication date: August 13, 2020
    Inventors: TOSHIAKI ONO, SATOKO IIDA, TOMOHIKO ASATSUMA, YOSHIAKI KITANO, YUSUKE MATSUMURA, RYOKO KAJIKAWA
  • Publication number: 20200176461
    Abstract: A silicon wafer is capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer according to the present invention is a silicon wafer in which there is formed a multilayered film constituting a semiconductor device layer on one main surface thereof in a device process, which is warped in a bowl shape due to an isotropic film stress of the multilayered film, and which has a (111) plane orientation.
    Type: Application
    Filed: June 6, 2018
    Publication date: June 4, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Toshiaki ONO, Bong-Gyun KO
  • Publication number: 20200105542
    Abstract: Provided is a method of accurately predicting the thermal donor formation behavior in a silicon wafer, a method of evaluating a silicon wafer using the prediction method, and a method of producing a silicon wafer using the evaluation method. The method of predicting the formation behavior of thermal donors, includes: a first step of setting an initial oxygen concentration condition before performing heat treatment on the silicon wafer for reaction rate equations based on both a bond-dissociation model of oxygen clusters associated with the diffusion of interstitial oxygen and a bonding model of oxygen clusters associated with the diffusion of oxygen dimers; a second step of calculating the formation rate of oxygen clusters formed through the heat treatment using the reaction rate equations; and a third step of calculating the formation rate of thermal donors formed through the heat treatment based on the formation rate of the oxygen clusters.
    Type: Application
    Filed: June 12, 2018
    Publication date: April 2, 2020
    Applicant: SUMCO Corporation
    Inventors: Kazuhisa Torigoe, Shigeru Umeno, Toshiaki Ono
  • Publication number: 20200091089
    Abstract: Provided is a silicon wafer manufacturing method capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer manufacturing method according to the present invention is provided with calculating a target thickness of the silicon wafer required for ensuring a warpage reduction amount of a silicon wafer warped during a device process from a relationship between an amount of warpage of a silicon wafer and a thickness thereof occurring due to application of the same film stress to a plurality of silicon wafers having mutually different thicknesses; and processing a silicon single crystal ingot to thereby manufacture silicon wafers having the target thickness.
    Type: Application
    Filed: June 6, 2018
    Publication date: March 19, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Bong-Gyun KO, Toshiaki ONO
  • Publication number: 20200083060
    Abstract: A silicon wafer having a BMD density of 5×108/cm3 or more and 2.5×1010/cm3 or less in a region of 80 ?m to 285 ?M from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.?X?1000° C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec. The time Y and the temperature X satisfy Y=7.88×1067×X?22.5.
    Type: Application
    Filed: June 19, 2018
    Publication date: March 12, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Toshiaki ONO, Shigeru UMENO
  • Publication number: 20200051817
    Abstract: A manufacturing method of an epitaxial silicon wafer includes: an epitaxial-film formation step for forming an epitaxial film made of silicon on a surface of a silicon wafer in a trichlorosilane gas atmosphere; and a nitrogen-concentration setting step for setting the nitrogen concentration of the surface of the epitaxial film through inward diffusion from a nitride film on the epitaxial film, the nitride film being formed by subjecting the silicon wafer provided with the epitaxial film through the epitaxial-film formation step to a heat treatment in a nitrogen atmosphere.
    Type: Application
    Filed: September 12, 2017
    Publication date: February 13, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Kazuya KODANI, Toshiaki ONO, Kazuhisa TORIGOE
  • Publication number: 20200020817
    Abstract: A method of manufacturing an epitaxial silicon wafer that includes growing a silicon single crystal ingot doped with a boron concentration of 2.7×1017 atoms/cm3 or more and 1.3×1019 atoms/cm3 or less by the CZ method; producing a silicon substrate by processing the silicon single crystal ingot; and forming an epitaxial layer on a surface of the silicon substrate. During growing of the silicon single crystal ingot, the pull-up conditions of the silicon single crystal ingot are controlled so that the boron concentration Y (atoms/cm3) and an initial oxygen concentration X (×1017 atoms/cm3) satisfy the expression X??4.3×10?19Y+16.3.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Applicant: SUMCO CORPORATION
    Inventors: Kazuhisa TORIGOE, Toshiaki ONO
  • Publication number: 20190352796
    Abstract: Provided is a method of producing a high resistance n-type silicon single crystal ingot with small tolerance margin on resistivity in the crystal growth direction, which is suitably used in a power device. In the method of producing a silicon single crystal ingot using Sb or As as an n-type dopant, while a silicon single crystal ingot is pulled up, the amount of the n-type dopant being evaporated from a silicon melt per unit solidification ratio is kept within a target evaporation amount range per unit solidification ratio by controlling one or more pulling condition values including at least one of the pressure in a chamber, the flow volume of Ar gas, and a gap between a guide portion and the silicon melt.
    Type: Application
    Filed: January 11, 2018
    Publication date: November 21, 2019
    Applicant: SUMCO CORPORATION
    Inventors: Masataka HOURAI, Wataru SUGIMURA, Toshiaki ONO, Toshiyuki FUJIWARA
  • Publication number: 20190037160
    Abstract: At least one solid-state image pickup element includes a plurality of pixels that are arranged in a two-dimensional manner. Each of the plurality of pixels includes a plurality of photoelectric conversion units each including a pixel electrode, a photoelectric conversion layer disposed on the pixel electrode, and a counter electrode disposed such that the photoelectric conversion layer is sandwiched between the pixel electrode and the counter electrode. In one or more embodiments, each of the plurality of pixels also includes a microlens disposed on the plurality of photoelectric conversion units.
    Type: Application
    Filed: October 1, 2018
    Publication date: January 31, 2019
    Inventors: Toshiaki Ono, Masatsugu Itahashi, Naoki Inatani, Yu Maehashi, Hidekazu Takahashi
  • Patent number: 10192754
    Abstract: A method for producing an epitaxial silicon wafer, including a preliminary thermal treatment step of subjecting a silicon wafer to thermal treatment for increasing a density of oxygen precipitates, the silicon wafer being one that has an oxygen concentration in a range of 9×1017 atoms/cm3 to 16×1017 atoms/cm3, contains no dislocation cluster and no COP, and contains an oxygen precipitation suppression region, and an epitaxial layer forming step of forming an epitaxial layer on a surface of the silicon wafer after the preliminary thermal treatment step. The production method further includes a thermal treatment condition determining step of determining a thermal treatment condition in the preliminary thermal treatment step, based on a ratio of the oxygen precipitation suppression region of the silicon wafer before the preliminary thermal treatment step is carried out.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: January 29, 2019
    Assignee: SUMCO CORPORATION
    Inventors: Jun Fujise, Toshiaki Ono
  • Publication number: 20180337306
    Abstract: A manufacturing method for a group III nitride semiconductor substrate is provided with a first step of forming a second group III nitride semiconductor layer on a substrate; a second step of forming a protective layer on the second group III nitride semiconductor layer; a third step of selectively forming pits on dislocation portions of the second group III nitride semiconductor layer by gas-phase etching applied to the protective layer and the second group III nitride semiconductor layer; and a fourth step of forming a third group III nitride semiconductor layer on the second group III nitride semiconductor layer and/or the remaining protective layer so as to allow the pits to remain.
    Type: Application
    Filed: November 1, 2016
    Publication date: November 22, 2018
    Applicant: SUMCO CORPORATION
    Inventors: Koji MATSUMOTO, Toshiaki ONO, Hiroshi AMANO, Yoshio HONDA
  • Patent number: 10136091
    Abstract: At least one solid-state image pickup element includes a plurality of pixels that are arranged in a two-dimensional manner. Each of the plurality of pixels includes a plurality of photoelectric conversion units each including a pixel electrode, a photoelectric conversion layer disposed on the pixel electrode, and a counter electrode disposed such that the photoelectric conversion layer is sandwiched between the pixel electrode and the counter electrode. In one or more embodiments, each of the plurality of pixels also includes a microlens disposed on the plurality of photoelectric conversion units.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 20, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiaki Ono, Masatsugu Itahashi, Naoki Inatani, Yu Maehashi, Hidekazu Takahashi
  • Patent number: 10110797
    Abstract: Provided is an imaging device that includes a pixel unit in which each of a plurality of pixels includes m photoelectric conversion units and each of at least a part of the plurality of pixels outputs a first signal based on signal charges of n photoelectric conversion unit or units, where n is less than m; an adder unit configured to add a plurality of first signals output from a plurality of pixels different from each other; a determination unit configured to compare each of the plurality of first signals and a predetermined threshold to determine whether or not the plurality of first signals added by the adder unit include a signal larger than a predetermined threshold; and an output unit configured to output a determination result and the added signal.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: October 23, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Toshiaki Ono
  • Publication number: 20180294307
    Abstract: Each of a plurality of pixels arranged in two dimensions includes a photoelectric conversion unit including a pixel electrode, a photoelectric conversion layer provided above the pixel electrode, and a counter electrode provided so as to sandwich the photoelectric conversion layer between the counter electrode and the pixel electrode, and a microlens arranged above the photoelectric conversion unit. The plurality of pixels includes a first pixel and a plurality of second pixels. At least either the pixel electrodes of the plurality of second pixels are smaller than the pixel electrode of the first pixel or the counter electrodes of the plurality of second pixels are smaller than the counter electrode of the first pixel, and a configuration between the counter electrode and the microlens of the first pixel is the same as a configuration between the counter electrode and the microlens of each of the plurality of second pixels.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: Masatsugu Itahashi, Toshiaki Ono, Hidekazu Takahashi, Naoki Inatani, Yu Maehashi
  • Patent number: 10084980
    Abstract: A solid-state image sensor includes an image sensing unit in which a plurality of pixels are arrayed, a plurality of readout units configured to read out signals from the image sensing unit, a detector configured to detect an occurrence of a latch-up in each of the plurality of readout units, and a controller configured to control power supply to the plurality of readout units. The plurality of readout units are configured to read out signals from a same pixel in the image sensing unit. The controller is configured to shut off power supply to at least part of a readout unit in which the occurrence of the latch-up has been detected out of the plurality of readout units and thereafter supply power to the at least part.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: September 25, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Moriyama, Kazuaki Tashiro, Tatsuhito Goden, Toshiaki Ono