Abstract: Provided is a method of producing a high resistance n-type silicon single crystal ingot with small tolerance margin on resistivity in the crystal growth direction, which is suitably used in a power device. In the method of producing a silicon single crystal ingot using Sb or As as an n-type dopant, while a silicon single crystal ingot is pulled up, the amount of the n-type dopant being evaporated from a silicon melt per unit solidification ratio is kept within a target evaporation amount range per unit solidification ratio by controlling one or more pulling condition values including at least one of the pressure in a chamber, the flow volume of Ar gas, and a gap between a guide portion and the silicon melt.

Abstract: At least one solid-state image pickup element includes a plurality of pixels that are arranged in a two-dimensional manner. Each of the plurality of pixels includes a plurality of photoelectric conversion units each including a pixel electrode, a photoelectric conversion layer disposed on the pixel electrode, and a counter electrode disposed such that the photoelectric conversion layer is sandwiched between the pixel electrode and the counter electrode. In one or more embodiments, each of the plurality of pixels also includes a microlens disposed on the plurality of photoelectric conversion units.

Abstract: A method for producing an epitaxial silicon wafer, including a preliminary thermal treatment step of subjecting a silicon wafer to thermal treatment for increasing a density of oxygen precipitates, the silicon wafer being one that has an oxygen concentration in a range of 9×1017 atoms/cm3 to 16×1017 atoms/cm3, contains no dislocation cluster and no COP, and contains an oxygen precipitation suppression region, and an epitaxial layer forming step of forming an epitaxial layer on a surface of the silicon wafer after the preliminary thermal treatment step. The production method further includes a thermal treatment condition determining step of determining a thermal treatment condition in the preliminary thermal treatment step, based on a ratio of the oxygen precipitation suppression region of the silicon wafer before the preliminary thermal treatment step is carried out.

Abstract: A manufacturing method for a group III nitride semiconductor substrate is provided with a first step of forming a second group III nitride semiconductor layer on a substrate; a second step of forming a protective layer on the second group III nitride semiconductor layer; a third step of selectively forming pits on dislocation portions of the second group III nitride semiconductor layer by gas-phase etching applied to the protective layer and the second group III nitride semiconductor layer; and a fourth step of forming a third group III nitride semiconductor layer on the second group III nitride semiconductor layer and/or the remaining protective layer so as to allow the pits to remain.

Abstract: At least one solid-state image pickup element includes a plurality of pixels that are arranged in a two-dimensional manner. Each of the plurality of pixels includes a plurality of photoelectric conversion units each including a pixel electrode, a photoelectric conversion layer disposed on the pixel electrode, and a counter electrode disposed such that the photoelectric conversion layer is sandwiched between the pixel electrode and the counter electrode. In one or more embodiments, each of the plurality of pixels also includes a microlens disposed on the plurality of photoelectric conversion units.

Abstract: Provided is an imaging device that includes a pixel unit in which each of a plurality of pixels includes m photoelectric conversion units and each of at least a part of the plurality of pixels outputs a first signal based on signal charges of n photoelectric conversion unit or units, where n is less than m; an adder unit configured to add a plurality of first signals output from a plurality of pixels different from each other; a determination unit configured to compare each of the plurality of first signals and a predetermined threshold to determine whether or not the plurality of first signals added by the adder unit include a signal larger than a predetermined threshold; and an output unit configured to output a determination result and the added signal.

Abstract: Each of a plurality of pixels arranged in two dimensions includes a photoelectric conversion unit including a pixel electrode, a photoelectric conversion layer provided above the pixel electrode, and a counter electrode provided so as to sandwich the photoelectric conversion layer between the counter electrode and the pixel electrode, and a microlens arranged above the photoelectric conversion unit. The plurality of pixels includes a first pixel and a plurality of second pixels. At least either the pixel electrodes of the plurality of second pixels are smaller than the pixel electrode of the first pixel or the counter electrodes of the plurality of second pixels are smaller than the counter electrode of the first pixel, and a configuration between the counter electrode and the microlens of the first pixel is the same as a configuration between the counter electrode and the microlens of each of the plurality of second pixels.

Abstract: A solid-state image sensor includes an image sensing unit in which a plurality of pixels are arrayed, a plurality of readout units configured to read out signals from the image sensing unit, a detector configured to detect an occurrence of a latch-up in each of the plurality of readout units, and a controller configured to control power supply to the plurality of readout units. The plurality of readout units are configured to read out signals from a same pixel in the image sensing unit. The controller is configured to shut off power supply to at least part of a readout unit in which the occurrence of the latch-up has been detected out of the plurality of readout units and thereafter supply power to the at least part.

Abstract: An epitaxial silicon wafer is provided with a boron-doped silicon substrate and an epitaxial layer formed on a surface of the silicon substrate, wherein the boron concentration in the silicon substrate is 2.7×1017 atoms/cm3 or more and 1.3×1019 atoms/cm3 or less, and an initial oxygen concentration in the silicon substrate is 11×1017 atoms/cm3 or less. When an oxygen precipitate evaluation heat treatment, such as a heat treatment at 700° C. for 3 hours and a heat treatment at 1,000° C. for 16 hours is executed on the epitaxial silicon wafer, the density of oxygen precipitate in the silicon substrate is 1×1010/cm3 or less.

Abstract: An epitaxial silicon wafer includes a silicon wafer consisting of a COP region in which a nitrogen concentration is 1×108?3×109 atoms/cm3, and an epitaxial silicon film formed on the silicon wafer. When heat treatment for evaluation is applied, a density of BMD formed inside the silicon wafer is 1×108?3×109 atoms/cm3 over the entire radial direction of the silicon wafer. An average density of the BMD formed in an outer peripheral region of the silicon wafer which is a 1-10 mm range separated inward from an outermost periphery thereof is lower than the average density of the BMD formed in a center region. A variation in the BMD density in the outer peripheral region is 3 or less, and a residual oxygen concentration in the outer peripheral region is 8×1017 atoms/cm3 or more.

Abstract: An epitaxial silicon wafer includes a silicon wafer consisting of a COP region in which a nitrogen concentration is 1×1012?1×1013 atoms/cm3, and an epitaxial silicon film formed on the silicon wafer. When heat treatment for evaluation is applied, a density of BMD formed inside the silicon wafer is 1×108?3×109 atoms/cm3 over the entire radial direction of the silicon wafer. An average density of the BMD formed in an outer peripheral region of the silicon wafer which is a 1-10 mm range separated inward from an outermost periphery thereof is lower than the average density of the BMD formed in a center region. A variation in the BMD density in the outer peripheral region is 3 or less, and a residual oxygen concentration in the outer peripheral region is 8×1017 atoms/cm3 or more.

Abstract: Each of a plurality of pixels arranged in two dimensions includes a photoelectric conversion unit including a pixel electrode, a photoelectric conversion layer provided above the pixel electrode, and a counter electrode provided so as to sandwich the photoelectric conversion layer between the counter electrode and the pixel electrode, and a microlens arranged above the photoelectric conversion unit. The plurality of pixels includes a first pixel and a plurality of second pixels. At least either the pixel electrodes of the plurality of second pixels are smaller than the pixel electrode of the first pixel or the counter electrodes of the plurality of second pixels are smaller than the counter electrode of the first pixel, and a configuration between the counter electrode and the microlens of the first pixel is the same as a configuration between the counter electrode and the microlens of each of the plurality of second pixels.

Abstract: After determining the precipitated oxygen concentration and the residual oxygen concentration in a silicon wafer after heat treatment performed in a device fabrication process; the critical shear stress ?cri at which slip dislocations are formed in the silicon wafer in the device fabrication process is determined based on the obtained precipitated oxygen concentration and residual oxygen concentration; and the obtained critical shear stress ?cri and the thermal stress ? applied to the silicon wafer in the heat treatment of the device fabrication process are compared, thereby determining that slip dislocations are formed in the silicon wafer in the device fabrication process when the thermal stress ? is equal to or more than the critical shear stress ?cri, or determining that slip dislocations are not formed in the silicon wafer in the device fabrication process when the thermal stress ? is less than the critical shear stress ?cri.

Abstract: A method of manufacturing an epitaxial wafer, including a silicon substrate having a surface sliced from single-crystalline silicon and a silicon epitaxial layer deposited on the surface of the silicon substrate, includes an oxygen concentration controlling heat treatment process in which a heat treatment of the epitaxial layer is performed under a non-oxidizing atmosphere after the epitaxial growth such that an oxygen concentration of the surface of the silicon epitaxial layer is set to 1.0×1017 to 12×1017 atoms/cm3 (ASTM F-121, 1979).

Abstract: Ones of row addresses and column addresses of pixels in a first group are the same as those of a second group. A range of the others of the row addresses and the column addresses of the first group excludes that of the second group. A range of the others of row addresses and column addresses is included in a range of the others of the row addresses and the column addresses of the first and second groups. A portion of the range of the row addresses and the column addresses of the first group overlaps with that of the third group, and the other portion of the range of the first group does not overlap with that of the third group. Intra-group addition signals of the first, second, and third groups are obtained.

Abstract: A manufacturing method of an epitaxial silicon wafer including a silicon wafer doped with boron and having a resistivity of 100 m?·cm or less and an epitaxial film formed on the silicon wafer includes: growing the epitaxial film on the silicon wafer; and applying a heat treatment on the epitaxial silicon wafer at a temperature of less than 900 degrees C.

Abstract: An image sensor includes a readout unit having a plurality of circuit blocks. At least a part of each of the plurality of circuit blocks is arranged in each of a plurality of regions electrically isolated from each other. When latchup has occurred in a circuit block of the plurality of circuit blocks, the voltage supply unit shuts off supply of a power supply voltage to the region in which the part is arranged, and then performs the supply of the power supply voltage to the region in which the part is arranged, and the voltage supply unit supplies the power supply voltage to the region in which the circuit block without latchup is arranged, while shutting off the supply of the power supply voltage to the region in which the part is arranged.

Abstract: After determining the size of oxygen precipitates and the residual oxygen concentration in a silicon wafer after heat treatment performed in a device fabrication process; the critical shear stress ?cri at which slip dislocations are formed in the silicon wafer in the device fabrication process is determined based on the obtained size of the oxygen precipitates and residual oxygen concentration; and the obtained critical shear stress ?cri and the thermal stress ? applied to the silicon wafer in the heat treatment of the device fabrication process are compared, thereby determining that slip dislocations are formed in the silicon wafer in the device fabrication process when the thermal stress ? is equal to or more than the critical shear stress ?cri, or determining that slip dislocations are not formed in the silicon wafer in the device fabrication process when the thermal stress ? is less than the critical shear stress ?cri.

Abstract: The present invention relates to a technology for providing a selection unit configured to perform selection of a bit memory that holds a signal of a first bit of a digital signal from among a plurality of bit memories commonly in a memory unit in each of a plurality of AD conversion units.

Abstract: A method for producing an epitaxial silicon wafer, including a preliminary thermal treatment step of subjecting a silicon wafer to thermal treatment for increasing a density of oxygen precipitates, the silicon wafer being one that has an oxygen concentration in a range of 9×1017 atoms/cm3 to 16×1017 atoms/cm3, contains no dislocation cluster and no COP, and contains an oxygen precipitation suppression region, and an epitaxial layer forming step of forming an epitaxial layer on a surface of the silicon wafer after the preliminary thermal treatment step. The production method further includes a thermal treatment condition determining step of determining a thermal treatment condition in the preliminary thermal treatment step, based on a ratio of the oxygen precipitation suppression region of the silicon wafer before the preliminary thermal treatment step is carried out.