Patents by Inventor Toshiaki Ono
Toshiaki Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11159756Abstract: At least one solid-state image pickup element includes a plurality of pixels that are arranged in a two-dimensional manner. Each of the plurality of pixels includes a plurality of photoelectric conversion units each including a pixel electrode, a photoelectric conversion layer disposed on the pixel electrode, and a counter electrode disposed such that the photoelectric conversion layer is sandwiched between the pixel electrode and the counter electrode. In one or more embodiments, each of the plurality of pixels also includes a microlens disposed on the plurality of photoelectric conversion units.Type: GrantFiled: October 1, 2018Date of Patent: October 26, 2021Assignee: CANON KABUSHIKI KAISHAInventors: Toshiaki Ono, Masatsugu Itahashi, Naoki Inatani, Yu Maehashi, Hidekazu Takahashi
-
Publication number: 20210320177Abstract: A silicon wafer having a layer of oxygen precipitates and method of manufacturing thereof wherein the wafer exhibiting robustness characterized as having a ratio of a first average density from a first treatment that to a second average density from a second treatment is between 0.74 to 1.02, wherein the first treatment includes heating the wafer or a portion of the wafer at about 1150° C. for about 2 minutes and then between about 950 to 1000° C. for about 16 hours, and the second treatment includes heating the wafer or a portion of the wafer at about 780° C. for about 3 hours and then between about 950 to 1000° C. for about 16 hours. The wafer exhibits heretofore unattainable uniformity wherein a ratio of an oxygen precipitate density determined from any one cubic centimeter in the BMD layer of the wafer to another oxygen precipitate density from any other one cubic centimeter in the BMD layer of the wafer is in a range of 0.77 to 1.30.Type: ApplicationFiled: April 8, 2021Publication date: October 14, 2021Applicant: SUMCO CORPORATIONInventors: Kazuhisa TORIGOE, Toshiaki ONO, Shunya KAWAGUCHI
-
Publication number: 20210296382Abstract: A solid-state imaging device according to an embodiment of the present disclosure includes a stacked photoelectric converter for each of pixels. The stacked photoelectric converter has a plurality of photoelectric conversion elements stacked therein. The plurality of photoelectric conversion elements each has different wavelength selectivity. This solid-state imaging device further includes a plurality of data output lines from which pixel signals based on electric charges outputted from the photoelectric conversion elements are outputted. A plurality of data output lines is provided for each predetermined unit pixel column. The plurality of the data output lines is equal in number to an integer multiple of the photoelectric conversion elements stacked in the stacked photoelectric converter.Type: ApplicationFiled: July 9, 2019Publication date: September 23, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Toshiaki ONO
-
Patent number: 11121003Abstract: Provided is a method of accurately predicting the thermal donor formation behavior in a silicon wafer, a method of evaluating a silicon wafer using the prediction method, and a method of producing a silicon wafer using the evaluation method. The method of predicting the formation behavior of thermal donors, includes: a first step of setting an initial oxygen concentration condition before performing heat treatment on the silicon wafer for reaction rate equations based on both a bond-dissociation model of oxygen clusters associated with the diffusion of interstitial oxygen and a bonding model of oxygen clusters associated with the diffusion of oxygen dimers; a second step of calculating the formation rate of oxygen clusters formed through the heat treatment using the reaction rate equations; and a third step of calculating the formation rate of thermal donors formed through the heat treatment based on the formation rate of the oxygen clusters.Type: GrantFiled: June 12, 2018Date of Patent: September 14, 2021Assignee: SUMCO CorporationInventors: Kazuhisa Torigoe, Shigeru Umeno, Toshiaki Ono
-
Publication number: 20210265402Abstract: A solid-state image sensor includes a plurality of imaging device blocks each including P×Q imaging devices. In an imaging device block, first charge movement controlling electrodes are provided between the imaging devices, and second charge movement controlling electrodes are provided between the imaging device blocks. In the imaging device block, P imaging devices are arrayed along a first direction, and Q imaging devices are arrayed along a second direction. Charge accumulated in a photoelectric conversion layer of the (P?1)th imaging device from the first imaging device along the first direction is transferred to the photoelectric conversion layer of the Pth imaging device and read out together with charge accumulated in the photoelectric conversion layers of the Q Pth imaging devices, under the control of the first charge movement controlling electrodes.Type: ApplicationFiled: June 7, 2019Publication date: August 26, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Toshiaki ONO
-
Patent number: 11094557Abstract: A silicon wafer having a BMD density of 5×108/cm3 or more and 2.5×1010/cm3 or less in a region of 80 ?m to 285 ?m from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.?X?1000° C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec. The time Y and the temperature X satisfy Y=7.88×1067×X?22.5.Type: GrantFiled: June 19, 2018Date of Patent: August 17, 2021Assignee: SUMCO CORPORATIONInventors: Toshiaki Ono, Shigeru Umeno
-
Patent number: 11078595Abstract: Provided is a method of producing a high resistance n-type silicon single crystal ingot with small tolerance margin on resistivity in the crystal growth direction, which is suitably used in a power device. In the method of producing a silicon single crystal ingot using Sb or As as an n-type dopant, while a silicon single crystal ingot is pulled up, the amount of the n-type dopant being evaporated from a silicon melt per unit solidification ratio is kept within a target evaporation amount range per unit solidification ratio by controlling one or more pulling condition values including at least one of the pressure in a chamber, the flow volume of Ar gas, and a gap between a guide portion and the silicon melt.Type: GrantFiled: January 11, 2018Date of Patent: August 3, 2021Assignee: SUMCO CORPORATIONInventors: Masataka Hourai, Wataru Sugimura, Toshiaki Ono, Toshiyuki Fujiwara
-
Publication number: 20210210340Abstract: A manufacturing method allows growth of a group III nitride semiconductor layer on a Si substrate with an AlN buffer layer interposed between same, so as to suppress group III material from diffusing into the Si substrate. The group III nitride semiconductor substrate manufacturing method includes: a step of forming an AlN coating on the inside of a furnace; steps of installing an Si substrate in the furnace covered with the AlN coating and forming an AlN buffer layer on the Si substrate; and a step of forming a group III nitride semiconductor layer on the AN buffer layer.Type: ApplicationFiled: March 5, 2019Publication date: July 8, 2021Applicant: SUMCO CORPORATIONInventors: Koji MATSUMOTO, Toshiaki ONO, Hiroshi AMANO, Yoshio HONDA
-
Publication number: 20210202545Abstract: A solid-state imaging element which detects visible light and ultraviolet light in one pixel provides improved resolution. First and second photoelectric conversion elements each perform photoelectric conversion. of incident light. A first accumulation part accumulates electric charges that are photoelectrically converted by the first photoelectric conversion element. second accumulation part is disposed on one face of a substrate and accumulates electric charges that are photoelectrically converted by the second photoelectric conversion element. A connection part is connected to the second accumulation part and transfers the electric charges accumulated in the second accumulation part to another face of the substrate.Type: ApplicationFiled: September 2, 2019Publication date: July 1, 2021Inventors: SATOKO IIDA, YOSHIAKI KITANO, KENGO NAGATA, TOSHIAKI ONO, TOMOHIKO ASATSUMA
-
Publication number: 20210151314Abstract: Diffusion of a group III material into an Si substrate is suppressed during the time when a group III nitride semiconductor layer is grown on the Si substrate, with an AlN buffer layer being interposed therebetween. A method for manufacturing a group III nitride semiconductor substrate comprises: a step for growing a first AlN buffer layer on an Si substrate; a step for growing a second AlN buffer layer on the first AlN buffer layer at a temperature higher than a growth temperature of the first AlN buffer layer; and a step for growing a group III nitride semiconductor layer on the second AlN buffer layer. The growth temperature of the first AlN buffer layer is 400-600° C.Type: ApplicationFiled: October 2, 2018Publication date: May 20, 2021Applicant: SUMCO CORPORATIONInventors: Koji MATSUMOTO, Toshiaki ONO, Hiroshi AMANO, Yoshio HONDA
-
Patent number: 10910328Abstract: Provided is a silicon wafer manufacturing method capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer manufacturing method according to the present invention is provided with calculating a target thickness of the silicon wafer required for ensuring a warpage reduction amount of a silicon wafer warped during a device process from a relationship between an amount of warpage of a silicon wafer and a thickness thereof occurring due to application of the same film stress to a plurality of silicon wafers having mutually different thicknesses; and processing a silicon single crystal ingot to thereby manufacture silicon wafers having the target thickness.Type: GrantFiled: June 6, 2018Date of Patent: February 2, 2021Assignee: SUMCO CORPORATIONInventors: Bong-Gyun Ko, Toshiaki Ono
-
Publication number: 20200399780Abstract: A convection pattern estimation method of a silicon melt includes: applying a horizontal magnetic field of 0.2 tesla or more to a silicon melt in a rotating quartz crucible with use of a pair of magnetic bodies disposed across the quartz crucible; before a seed crystal is dipped into the silicon melt to which the horizontal magnetic field is applied; measuring temperatures at a first and second measurement points positioned on a first imaginary line that passes through a center of a surface of the silicon melt and is not in parallel with a central magnetic field line of the horizontal magnetic field as viewed vertically from above; and estimating a direction of a convection flow in a plane in the silicon melt orthogonal to the direction in which the horizontal magnetic field is applied on a basis of the measured temperatures of the first and second measurement points.Type: ApplicationFiled: February 27, 2019Publication date: December 24, 2020Applicant: SUMCO CORPORATIONInventors: Wataru SUGIMURA, Ryusuke YOKOYAMA, Toshiyuki FUJIWARA, Toshiaki ONO
-
Patent number: 10861990Abstract: A method of manufacturing an epitaxial silicon wafer that includes growing a silicon single crystal ingot doped with a boron concentration of 2.7×1017 atoms/cm3 or more and 1.3×1019 atoms/cm3 or less by the CZ method; producing a silicon substrate by processing the silicon single crystal ingot; and forming an epitaxial layer on a surface of the silicon substrate. During growing of the silicon single crystal ingot, the pull-up conditions of the silicon single crystal ingot are controlled so that the boron concentration Y (atoms/cm3) and an initial oxygen concentration X (×1017 atoms/cm3) satisfy the expression X??4.3×10?19Y+16.3.Type: GrantFiled: September 26, 2019Date of Patent: December 8, 2020Assignee: SUMCO CORPORATIONInventors: Kazuhisa Torigoe, Toshiaki Ono
-
Patent number: 10777704Abstract: A manufacturing method for a group III nitride semiconductor substrate is provided with a first step of forming a second group III nitride semiconductor layer on a substrate; a second step of forming a protective layer on the second group III nitride semiconductor layer; a third step of selectively forming pits on dislocation portions of the second group III nitride semiconductor layer by gas-phase etching applied to the protective layer and the second group III nitride semiconductor layer; and a fourth step of forming a third group III nitride semiconductor layer on the second group III nitride semiconductor layer and/or the remaining protective layer so as to allow the pits to remain.Type: GrantFiled: November 1, 2016Date of Patent: September 15, 2020Assignee: SUMCO CORPORATIONInventors: Koji Matsumoto, Toshiaki Ono, Hiroshi Amano, Yoshio Honda
-
SOLID-STATE IMAGING ELEMENT, METHOD OF DRIVING SOLID-STATE IMAGING ELEMENT, AND ELECTRONIC APPARATUS
Publication number: 20200260026Abstract: Provided is a solid-state imaging element configured to automatically extend dynamic range for each unit pixel. A solid-state imaging element includes, for a unit pixel, a first photoelectric conversion element, a first accumulation portion that accumulates electric charge obtained by photoelectric conversion by the first photoelectric conversion element, and a first film that is electrically connected to the first accumulation portion and has an optical characteristic changing according to applied voltage. Furthermore, the unit pixel of the solid-state imaging element can further include a first transfer transistor that transfers electric charge obtained by photoelectric conversion by the photoelectric conversion element to the first accumulation portion, an amplification transistor that is electrically connected to the first accumulation portion, and a selection transistor that is electrically connected to the amplification transistor.Type: ApplicationFiled: October 12, 2018Publication date: August 13, 2020Inventors: TOSHIAKI ONO, SATOKO IIDA, TOMOHIKO ASATSUMA, YOSHIAKI KITANO, YUSUKE MATSUMURA, RYOKO KAJIKAWA -
Publication number: 20200176461Abstract: A silicon wafer is capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer according to the present invention is a silicon wafer in which there is formed a multilayered film constituting a semiconductor device layer on one main surface thereof in a device process, which is warped in a bowl shape due to an isotropic film stress of the multilayered film, and which has a (111) plane orientation.Type: ApplicationFiled: June 6, 2018Publication date: June 4, 2020Applicant: SUMCO CORPORATIONInventors: Toshiaki ONO, Bong-Gyun KO
-
Publication number: 20200105542Abstract: Provided is a method of accurately predicting the thermal donor formation behavior in a silicon wafer, a method of evaluating a silicon wafer using the prediction method, and a method of producing a silicon wafer using the evaluation method. The method of predicting the formation behavior of thermal donors, includes: a first step of setting an initial oxygen concentration condition before performing heat treatment on the silicon wafer for reaction rate equations based on both a bond-dissociation model of oxygen clusters associated with the diffusion of interstitial oxygen and a bonding model of oxygen clusters associated with the diffusion of oxygen dimers; a second step of calculating the formation rate of oxygen clusters formed through the heat treatment using the reaction rate equations; and a third step of calculating the formation rate of thermal donors formed through the heat treatment based on the formation rate of the oxygen clusters.Type: ApplicationFiled: June 12, 2018Publication date: April 2, 2020Applicant: SUMCO CorporationInventors: Kazuhisa Torigoe, Shigeru Umeno, Toshiaki Ono
-
Publication number: 20200091089Abstract: Provided is a silicon wafer manufacturing method capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer manufacturing method according to the present invention is provided with calculating a target thickness of the silicon wafer required for ensuring a warpage reduction amount of a silicon wafer warped during a device process from a relationship between an amount of warpage of a silicon wafer and a thickness thereof occurring due to application of the same film stress to a plurality of silicon wafers having mutually different thicknesses; and processing a silicon single crystal ingot to thereby manufacture silicon wafers having the target thickness.Type: ApplicationFiled: June 6, 2018Publication date: March 19, 2020Applicant: SUMCO CORPORATIONInventors: Bong-Gyun KO, Toshiaki ONO
-
Publication number: 20200083060Abstract: A silicon wafer having a BMD density of 5×108/cm3 or more and 2.5×1010/cm3 or less in a region of 80 ?m to 285 ?M from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.?X?1000° C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec. The time Y and the temperature X satisfy Y=7.88×1067×X?22.5.Type: ApplicationFiled: June 19, 2018Publication date: March 12, 2020Applicant: SUMCO CORPORATIONInventors: Toshiaki ONO, Shigeru UMENO
-
Publication number: 20200051817Abstract: A manufacturing method of an epitaxial silicon wafer includes: an epitaxial-film formation step for forming an epitaxial film made of silicon on a surface of a silicon wafer in a trichlorosilane gas atmosphere; and a nitrogen-concentration setting step for setting the nitrogen concentration of the surface of the epitaxial film through inward diffusion from a nitride film on the epitaxial film, the nitride film being formed by subjecting the silicon wafer provided with the epitaxial film through the epitaxial-film formation step to a heat treatment in a nitrogen atmosphere.Type: ApplicationFiled: September 12, 2017Publication date: February 13, 2020Applicant: SUMCO CORPORATIONInventors: Kazuya KODANI, Toshiaki ONO, Kazuhisa TORIGOE