Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.

Abstract: In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element.

Abstract: A semiconductor integrated circuit device has a plurality of emitter-coupled logic (ECL) gates. Separate power source wiring lines are provided for current switch circuits and emitter follower output circuits for the gates. The separate sets of power source wiring lines are respectively coupled to the corresponding external terminals of the semiconductor integrated circuit device. The power source wiring lines for each set are arranged adjacent one another on a semiconductor chip in order that they may be short circuited or kept separated depending upon the package structure of the semiconductor integrated circuit device.

Abstract: There is disclosed a decoder circuit applicable to a decoding circuit of a DRAM which is comprised of a differential amplifier, first and second differential amplification lines connected to the differential amplifier, a pair of P-channel transistors connected between the first and second lines to precharge them up to a predetermined voltage in response to a clock signal applied to gates thereof, and one N-channel transistor connected between the first line and a ground line the gate of which is connected to either of non-reversible and reversible address signal lines. There is also disclosed an address selection circuit as an application of the above mentioned decoder circuit.

Abstract: In a semiconductor memory device comprising memory cells in which first and second potentials correspond to the logic values "0" and "1", the first potential is closer to the second potential than the potential of unselected word lines, by 0.3 V or more. The pull-up transistor is of the N-type, and the pull-down transistor is of the P-type.

Abstract: Dummy power source wirings connected to a power source wiring are arranged in empty regions among the signal wirings that cross the clock wirings, the dummy power source wirings being arranged over or under the clock wirings in a manner to cross the clock wirings. The dummy power source wirings are formed to equalize the capacitances of the wirings whose lengths should be equalized among, for example, the clock distributing circuits or among the clock drivers.

Abstract: A nailing machine having a cylinder housing which houses a cylinder which slidably houses a piston in communication with a source of compressed fluid for moving the piston within the cylinder, and a nail machine body which integrally includes a grip portion. A nail magazine and a nail feeder cooperate to feed a nail to the injection portion of the nailing machine. A bumper is arranged to collide with the lower surface of the piston during the nailing operation. The cylinder housing is coupled with the nail machine body so as to be movable in a nail-driving direction. A nail driver is in communication and moves integrally with the piston. A compressed fluid communication chamber is formed between the grip portion and the nailing machine body to move the piston and thereby the nail drives in a nail-driving direction.

Abstract: In a semiconductor memory device comprising memory cells in which first and second potentials correspond to the logic values "0" and "1", the first potential is closer to the second potential than the potential of unselected word lines, by 0.3 V or more. The pull-up transistor is of the N-type, and the pull-down transistor is of the P-type.

Abstract: The device has an architecture for improving the degree of integration by an amount corresponding to the reduction rate of memory cells, in which a plurality of memory cells are formed above or below each of a plurality of sense amplifiers.

Abstract: Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.

Abstract: Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.

Abstract: A magnetic shielding material is described which has a laminate structure comprising a ferromagnetic sheet having a high saturation magnetic flux density, a ferromagnetic sheet having a high magnetic permeability and a non-magnetic sheet. The high saturation magnetic flux density sheet includes a sheet of mold steel, silicon steel or an iron-cobalt alloy. The high magnetic permeability sheet includes an amorphous alloy foil or a laminate thereof. The magnetic shielding material may further have at least one foil of an electromagnetic wave-shielding material.

Abstract: A method of evaluating properties of an oxygen sensor used for detecting air-fuel ratio of exhaust gas from internal combustion engine comprises steps of preparing a burnt gas having a predetermined excess air ratio, supplying additional oxidation gas and/or reduction gas into the burnt gas, and detecting an output from the sensor exposed to the mixed gas flow. The supply amount of the additional gas is increased and decreased with a frequency of at least 10 Hz, and a ratio of a supply increasing period to a supply decreasing period is changed to change the supply amount of the additional gas, so that an excess air ratio .lambda. can be controlled similarly to exhaust gas from an actual engine.

Abstract: Disclosed is a semiconductor memory device (DRAM) which includes a plurality of island regions, at least one cell transistor disposed on each island region and cylindrical capacitor surrounding said each island region. By so composing, the capacity of the cell capacitor incorporated into a small space can be increased.Also disclosed is method of fabricating a semiconductor memory device which includes a step of forming a groove having a necessary depth in a semiconductor substrate, a step of depositing a membrane excelling in coverage on it, a step of etching by an etching method having a strong anisotropy in the vertical direction while leaving said deposit membrane on sidewall, and a step of etching deeper the exposed portion of the semiconductor surface in the groove and forming capacity element and isolation region by using this deep trench.

Abstract: A MIS capacitor to be implemented in a semiconductor device employing various or predetermined circuits, has a dielectric side electrode which is in contact with a buried layer provided on a semiconductor substrate through a dielectric film and a buried layer-side electrode connected to the buried layer. The buried layer-side electrode of the MIS capacitor is connected to a low-impedance side of the circuit employed therewith. This structure, when connected as such, is capable of reducing the influence of noise attributed to an .alpha.-ray and thereby operating the circuit stably. The semiconductor device using a MIS capacitor invention is adaptable to an emitter follower circuit and various logic circuits for preventing malfunction resulting from .alpha.-ray radiation.

Abstract: A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.

Abstract: A control device for an industrial machine comprising a numerical control device and a programmable controller, the numerical control device comprising: a data processing section essentially comprising a memory and a central processing unit, for analyzing and operating input numerical data, outputs of the data processing section being used for performing numerical control of a machine to be controlled and of rotation of a spindle of the machine; a gear ratio data memory for storing gear ratio data of gears through which a spindle motor is coupled to a spindle head holding a tool, the gear ratio data being applied to the gear ratio data memory through a bus from the programmable controller adapted to perform sequence control of the machine; and synchronous operation controller for calculating actual speed of rotation of the tool through operation using the gear ratio data and a feedback signal of the spindle motor, and performing synchronous operation control of the tool and a feed shaft.

Abstract: The present invention relates to novel adenosine derivatives having the formula (I): ##STR1## wherein R is a lower alkyl group; R' is hydrogen or a lower alkyl group; X is a cycloalkyl group, an alkyl group having at least one hydroxy group, an alkyl group having at least one phenyl group, a bicycloalkyl group, a naphthylalkyl group, an acenaphthylenylalkyl group or a group of the formula (II) or (III); ##STR2## Z is hydrogen, a hydroxy group or a lower alkoxy group, Q is hydrogen or a hydroxy group, A is --CH.sub.2 --, --O--, --S-- or shows a direct connection; Y is --(CH.sub.2).sub.n -- or shows a direct connection; n is an integer of 1 to 3; and the broken line is a double bond or a single bond.and pharmaceutically acceptable salt thereof, which are useful as antihypertensive agents.

Abstract: A transistor circuit of this invention comprises a first transistor for receiving a first bias at its base, resistor means connected to the collector of the first transistor and clamp means connected to the junction between the first transistor and the resistor means, and obtains an output from a terminal of the resistor on the opposite to its junction with the first transistor. When a noise current due to .alpha. rays develops in the first transistor and the output is lowered, the clamp means operates in such a manner that the current flows through the clamp means and prevents the change of the output. The transistor circuit of this invention is connected to a resistor or a transistor and operates as a constant current circuit for supplying a current to the resistor or the transistor so that the current flowing therethrough becomes constant. For example, it is used as a constant current source of an emitter follower to constitute a level shift circuit.

Abstract: An ECL flip-flop circuit has a data holding differential transistor pair and a feedback circuit provided between the collectors and bases of this differential transistor pair. The feedback circuit includes a resistor connected between the bases of the data holding differential transistor pair, a pair of switching means for selectively terminating one end or the other of the resistor, and a pair of feedback transistors each adapted to receive at its base the collector potential of one transistor or the other of the differential transistor pair and to form an emitter follower circuit with the resistor selectively included therein. Thus, it is possible to prevent a malfunction of the ECl flip-flop circuit due to .alpha.-particles or the like.