Abstract: A reference voltage generator is composed of a first constant-voltage generator consisting of three p-type MOS transistors for generating a first reference voltage Vref for use in the normal operation, which is independent of an external power-supply voltage VCC and of a second constant-voltage generator consisting of two p-type MOS transistors and one n-type MOS transistor for generating a second reference voltage Vrefbi for use in a burn-in acceleration test, which is dependent on VCC. The output of each of the constant-voltage generators is feedbacked to the other constant-voltage generator as its input. Two differential amplifiers and two output drivers output, as an internal reduced voltage Vint, the higher one of Vref and Vrefbi which are outputted from the reference voltage generator.

Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

Abstract: A gas flow pass has a gas flow direction deflecting member arranged in the gas flow pass for deflecting a gas flow direction outward with respect to a center of the gas flow pass, and a foreign substance trapping member arranged at a downstream position of the gas flow direction deflecting member and arranged on a part of or all of an inner surface of the gas flow pass. Therefore, it is possible to obtain the gas flow pass which can prevent a damage of the foreign substances in the gas flow and have a long term reliability.

Abstract: A CPU acting as a mother chip, in combination with a DRAM acting as a subsidiary chip, is mounted. A mode output circuit is able to set the storage capacity of the DRAM as well as the refresh cycle of the DRAM for forwarding to a mode input circuit of the CPU through a mode output terminal of the DRAM and a mode input terminal of the CPU. The CPU controls an address generator according to the data from the mode input circuit, to set the number of bits of address data for access to the DRAM according to the DRAM storage capacity and the DRAM refresh cycle.

Abstract: An amorphous metal alloy strip having enhanced magnetic properties consisting essentially of a composition mainly composed of Fe, Si, B, C and P having the formula (Fe.sub.a Si.sub.b B.sub.c C.sub.d).sub.100-x P.sub.x, wherein "a", "b", "c" and "d" are atomic percentages ranging from 70 to 86, 1 to 19, 7 to 20 and 0.02 to 4, respectively, with the proviso that the sum of "a", "b", "c" and "d" is equal to 100, and "x" is a weight percentage ranging from 0.003 to 0.1, said alloy strip having a thickness of 40 to 90 .mu.m and a width of not less than 20 mm. This amorphous metal alloy strip can be produced by a sinle-roll or twin-roll process under a specific cooling condition.

Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.

Abstract: A honeycomb structural body with improved spalling strength includes a plurality of passages aligned in its axial direction which are defined by partition walls. In the honeycomb structural body, a ratio of L/d is in a range of 0.4-1.3, where d is a diameter of an inscribed circle of the periphery of the honeycomb structural body on a plane perpendicular to its axial direction, and L is a length along the axial direction of the honeycomb structural body.

Abstract: A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for

Abstract: A ceramic honeycomb catalytic converter having a novel canning structure capable of stably retaining a thin-walled ceramic honeycomb catalyst within a metal casing for a long period. A retainer member in the form of a ceramic fiber mat is disposed between an inner peripheral surface of the casing and an outer peripheral surface of the honeycomb catalyst, in a compressed state to generate a surface pressure for retaining the honeycomb catalyst in place. The ceramic fiber mat is composed of heat resistant and non-intumescent ceramic fibers, and has a compression characteristic which is substantially free from a significant increase or decrease over an operative temperature range of the catalytic converter. The casing may be provided with at least one locking member for locking the ceramic fiber mat in a flow direction of exhaust gas passed through the honeycomb catalyst.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: The present invention relates to adenosinedeaminase inhibitors containing at least one O-alkylated moiety derivative and the pharmaceutically acceptable salts thereof. The pharmaceutical compositions of the present invention include adenosinedeaminase inhibitors containing at least one of the compounds represented by Formula (I): ##STR1## wherein each of R.sub.1, R.sub.2, and R.sub.3 are the same or different and is hydrogen or alkyl;R is hydrogen, alkyl, alkenyl, alkynyl, hydroxyalkynyl, alkoxy, phenyl, hydroxy, amino, alkylamino, phenylamino or halogen;X is hydrogen, alkyl, alkynyl, allyl, methallyl, cycloalkyl, alkyl having one or more hydroxy groups, phenyl, substituted phenyl, alkyl having one or more phenyl groups, alkyl having one or more substituted phenyl groups, bicycloalkyl, naphthylalkyl, acenaphthylenylalkyl or a compound represented by Formula (II) or Formula (III) ##STR2## wherein Z is hydrogen, hydroxy or lower alkoxy;Q is hydrogen or hydroxy;A is --CH.sub.

Abstract: A first p-type transmission MOS transistor with a gate connected to one of complementary input signal lines, a source connected to a first power supply and a drain connected to one of complementary output signal lines, is provided. A second p-type transmission MOS transistor with a gate connected to the other of the complementary input signal lines, a source connected to the first power supply and a drain connected to the other of the complementary output signal lines, is provided. A first capacitive element is connected between the gate and substrate of the first transmission MOS transistor. A second capacitive element is connected between the gate and substrate of the second transmission MOS transistor. At the time when signals are transmitted, the substrate voltage of the transmission MOS transistor is changed statically in synchronization with the input signal.

Abstract: An exhaust gas purifying filter for removing carbon particles from combustion exhaust gas, having a honeycomb structural body, flow passages that are sealed alternately at both ends by means of sealing portions to form checkerboard patterns. In the exhaust gas purifying filter according to the invention, lengths of the sealing portions formed in the flow passages of the honeycomb structural body vary randomly. An exhaust gas purifying apparatus utilizing the exhaust gas purifying filter according to the invention is also disclosed.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: The present invention relates to adenosine deaminase inhibitors containing at least one O-alkylated moiety and the pharmaceutically acceptable salts thereof.The pharmaceutical compositions of the present invention include adenosine deaminase inhibitors containing at least one of the compounds represented by Formula (I): ##STR1## wherein each of R.sub.1, R.sub.2, and R.sub.3 are the same or different and is hydrogen or alkyl;R is hydrogen, alkyl, alkenyl, alkynyl, hydroxyalkynyl, alkoxy, phenyl, hydroxy, amino, alkylamino, phenylamino or halogen;X is hydrogen, alkyl, alkynyl, allyl, methallyl, cycloalkyl, alkyl having one or more hydroxy groups, phenyl, substituted phenyl, alkyl having one or more phenyl groups, alkyl having one or more substituted phenyl groups, bicycloalkyl, naphthylalkyl, acenaphthylenylalkyl or a compound represented by Formula (II) or Formula (III) ##STR2## wherein Z is hydrogen, hydroxy or lower alkoxy; Q is hydrogen or hydroxy;A is --CH.sub.2 --, --O--, --S-- or a mere linkage;Y is (CH.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: The present invention comprises a plurality of semiconductor testing circuit chips 2 having an exclusive function of testing a plurality of one item of semiconductor integrated-circuit chips 1, a computer 3 for controlling the semiconductor testing circuit chips 2 and for collecting the test results, and a motherboard 4 on which the plurality of chips 1 to be tested and the plurality of testing circuit chips 2 are mounted so that the chips 1 to be tested are connected to the testing circuit chips 2. Since the major testing functions are incorporated into the testing circuit chips 2, the computer 3 for collecting the test results can sufficiently be composed of a low-price computer, so that it is possible to greatly lower the price of the semiconductor testing apparatus. By increasing the number of the testing circuit chips 2, it is possible to greatly increase the number of chips which can be tested simultaneously.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: In a semiconductor memory device comprising memory cells in which first and second potentials correspond to the logic values "0" and "1", the first potential is closer to the second potential than the potential of unselected word lines, by 0.3 V or more. The pull-up transistor is of the N-type, and the pull-down transistor is of the P-type.