Patents by Inventor Toshio Yamada

Toshio Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Canning structure and manufacturing method thereof
    Patent number: 7163662
    Abstract: A canning structure comprises a ceramic honeycomb structure before carrying a catalyst, fixed beforehand within a metal case by a holding material. An impermeable layer is provided on at least one edge plane in the longitudinal direction of the holding material. Thus, the holding material does not carry expensive catalyst at the time of carrying catalyst, and accordingly chipping and cracking of the ceramic honeycomb structure can be prevented at the time of transporting, the catalyst carrying process, the canning process, and handling in each of the processes.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: January 16, 2007
    Assignee: NGK Insulators, Ltd.
    Inventors: Toshio Yamada, Toshihiko Hijikata
  • Semiconductor integrated circuit and IC card
    Patent number: 7154804
    Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: December 26, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
  • Honeycomb structure, method for manufacturing honeycomb structure, and exhaust gas purification system using honeycomb structure
    Patent number: 7128961
    Abstract: There is disclosed a honeycomb structure which can be used as a filter for trapping/collecting particulates included in an exhaust gas and in which it is possible to remove ashes deposited inside without requiring any special mechanism or apparatus or without being detached from the exhaust system. The structure comprises a plurality of through channels 9 extending to an axial direction of a honeycomb structure, porous partition walls 7 separating through channels one another, and plugging portions 11; said plugging portion plugging predetermined through channels 9a at one end and the rest of through channels 9b at other end opposite to the plugged end of the predetermined through channels, wherein at least a part of predetermined crossing portions of the porous partition walls is discontinued to form a void portion 17 in each of the predetermined crossing portions.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: October 31, 2006
    Assignee: NGK Insulators, Ltd.
    Inventors: Ryuji Kai, Toshio Yamada
  • Method of manufacturing a semiconductor device and a semiconductor device
    Publication number: 20060214721
    Abstract: Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.
    Type: Application
    Filed: May 17, 2006
    Publication date: September 28, 2006
    Inventors: Hiroyuki Ikeda, Toshio Sasaki, Akinobu Watanabe, Toshio Yamada, Akihisa Uchida
  • Honeycomb stucture
    Publication number: 20060216465
    Abstract: There is provided a honeycomb structure which is excellent in such a resistance to thermal shock as to prevent generation of cracks or dissolved losses in partition wall intersections as critical damages for a filter and which is capable of securing a sufficient bonding strength to partition walls even in a case where plugging portions have a high porosity. A honeycomb structure includes: porous partition walls arranged to define cells connecting two end faces to each other; and plugging portions arranged to plug the cells in either end face. A porosity of each plugging portion is 50 to 90%, and an area of pores each having a sectional area of 0.15 mm2 or more is 30% or more of a total pore area, the sectional area occupying an arbitrary section including a central axis of the plugging portion.
    Type: Application
    Filed: March 17, 2006
    Publication date: September 28, 2006
    Applicant: NGK INSULATORS, LTD.
    Inventors: Ryuji Kai, Toshio Yamada
  • Ceramic honeycomb structure
    Publication number: 20060210764
    Abstract: A ceramic honeycomb structure includes a cell structure which includes a plurality of cells partitioned by porous partition walls and forming fluid channels, and an outer wall disposed on an outer circumferential surface of the cell structure and formed of a coating material including ceramic particles. The ceramic particles have an average particle size of 20 to 50 ?m, and a portion of the outer wall positioned on an outer side of a center portion of the outer wall in its thickness direction has a porosity lower than porosity of the center portion.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 21, 2006
    Applicant: NGK Insulators, LTD.
    Inventors: Toshio Yamada, Kanji Yamada
  • Semiconductor integrated circuit and IC card
    Publication number: 20060187734
    Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.
    Type: Application
    Filed: March 17, 2006
    Publication date: August 24, 2006
    Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
  • Semiconductor integrated circuit and IC card
    Publication number: 20060164906
    Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.
    Type: Application
    Filed: March 17, 2006
    Publication date: July 27, 2006
    Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
  • Method of manufacturing a semiconductor device
    Patent number: 7073147
    Abstract: Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: July 4, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hiroyuki Ikeda, Toshio Sasaki, Akinobu Watanabe, Toshio Yamada, Akihisa Uchida
  • Ceramic honeycomb structure and method of manufacturing the same
    Publication number: 20060112669
    Abstract: The ceramic honeycomb structure has a plurality of cells partitioned by porous partition walls and extending through the structure in an axial direction, one end portion of a predetermined cell is plugged with a plugging portion constituted of a plugging material with which the cell is filled, and the other end portion of a remaining cell is plugged with the plugging portion on a side opposite to the end portion of the predetermined cell. In the ceramic honeycomb structure, a sectional numerical aperture of the plugging portion in the vicinity of the partition wall is smaller than that of the plugging portion in the vicinity of a central axis, and a difference between the sectional numerical apertures is 10% or more.
    Type: Application
    Filed: October 19, 2005
    Publication date: June 1, 2006
    Applicant: NGK INSULATORS, LTD.
    Inventors: Toshio Yamada, Tatsuhiko Hatano
  • Semiconductor integrated circuit and IC card
    Patent number: 7046573
    Abstract: A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: May 16, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems, Co.,, Ltd.
    Inventors: Yoshio Takazawa, Toshio Yamada, Shinichi Ozawa, Takeo Kanai, Minoru Katoh, Koudou Yamauchi, Toshihiro Araki
  • Method for plugging a cell of a honeycomb structure and method for manufacturing a honeycomb plugged structure
    Patent number: 7033452
    Abstract: There are disclosed a method for plugging a cell of a honeycomb structure and a method for manufacturing a honeycomb plugged structure. By the methods, plug portion having arbitrary depth and/or shape can exactly and relatively easily be formed. There is disclosed the method for plugging cell 3 of a honeycomb structure 1 having a plurality of cells surrounded by partition walls and extending through an axial direction. In the method for plugging the cells of the honeycomb structure, plugging member 6 molded in predetermined shape is inserted into the cell 3, and the plugging member 6 is bonded to the peripheral partition walls 3 to form plug portions. There is also provided the method for manufacturing the honeycomb plugged structure, including the steps of: plugging at least a certain cells of the honeycomb structure by this plugging method.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: April 25, 2006
    Assignee: NGK Insulators, Ltd.
    Inventors: Toshio Yamada, Yasushi Noguchi
  • Honeycomb structure, method for manufacturing honeycomb structure, and exhaust gas purification system using honeycomb structure
    Patent number: 7008461
    Abstract: There is disclosed a honeycomb structure usable as a filter for trapping/collecting particulates included in an exhaust gas; and the structure can remove ashes deposited inside without requiring any special mechanism or apparatus or without being detached from the exhaust system. The structure includes: a plurality of through channels 9 extending to the axial direction of the honeycomb structure, porous partition walls 7 separating through channels one another, and plugging portions 11 plugging predetermined through channels 9a at one end and the rest of through channels 9b at other end opposite to the plugged end of the predetermined through channels, wherein a through-hole is formed in at least a part of the plugging portion, and its diameter is 0.2 mm or more, but not more than a value which is smaller between 1 mm and 75% of a diameter of an inscribed circle of the through channel.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: March 7, 2006
    Assignee: NGK Insulators, Ltd.
    Inventors: Tatsuyuki Kuki, Toshio Yamada
  • Semiconductor integrated circuit device
    Publication number: 20060023520
    Abstract: The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed.
    Type: Application
    Filed: June 30, 2005
    Publication date: February 2, 2006
    Inventors: Ryo Mori, Toshio Yamada, Tetsuya Muraya
  • Plugged honeycomb structure and method of manufacturing the same
    Publication number: 20050274096
    Abstract: There is disclosed a plugged honeycomb structure which can be easily regenerated with less cost and less energy consumption in a short time without changing an existing regeneration system. The plugged honeycomb structure includes: a honeycomb structure having partition walls formed of porous materials and a large number of cells defined•formed by the partition walls to constitute channels of a fluid; and a plugging portion which plugs any opening of the cell of the honeycomb structure. The structure further includes: a narrowed portion constituted in such a manner as to cover a part of an opening (non-plugged opening) which is not plugged by the plugging portion of the cell so that an open area of the non-plugged opening is reduced to be smaller than a channel sectional area of the cell.
    Type: Application
    Filed: May 31, 2005
    Publication date: December 15, 2005
    Applicant: NGK INSULATORS, LTD.
    Inventors: Toshio Yamada, Yasushi Noguchi
  • Semiconductor integrated circuit and method of manufacturing of semiconductor integrated circuit
    Patent number: 6967881
    Abstract: A semiconductor integrated circuit makes use of nonvolatile memory cells of a fuse circuit connected to a dedicated signal line without using a nonvolatile memory intended for general purpose use, which is connected to a common bus, in order to store control information for defect relief and the like of circuit modules. The reliability of storage of the control information is not limited to the performance of storage of information in the nonvolatile memory intended for general purpose use, and the reliability of storage of the control information can be easily enhanced. Since a second wiring used in the transfer of the control information is of a wiring dedicated for its transfer, it needs not perform switching between connections to circuit portions used for actual operations in the circuit modules and their control. A circuit configuration for delivering the control information can be simplified.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: November 22, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshio Sasaki, Toshio Yamada
  • Semiconductor device, a method of manufacturing the same and storage media
    Patent number: 6897496
    Abstract: Outside-cell wiring that extends the upper part of a macro cell to the direction of X axis is composed of the wiring layer of the upper layer than a terminal for a signal of the macro cell and this terminal is formed to extend in the direction of Y axis (direction that intersects the direction of X axis) so that the outside-cell wiring can be secured for a plurality of wiring channels. The macro cell and the outside-cell wiring are connected via this signal terminal.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: May 24, 2005
    Assignees: Hitachi, Ltd., Renesas Technology Corporation
    Inventors: Toshio Yamada, Kazumasa Yanagisawa, Yoshihiro Shinozaki, Hidetomo Aoyagi
  • High toughness amorphous alloy strip and production thereof
    Patent number: 6830636
    Abstract: A process of producing a high toughness iron-based amorphous alloy strip, using a single roll liquid quenching method, the strip having a thickness of more than 55 &mgr;m up to 100 &mgr;m and a width of 20 mm or more and having a fracture strain &egr;f satisfying the relationship &egr;f>0.1 where &egr;f=t/(D−t), t=thickness of the strip, and D=bent diameter upon fracture, &egr;f being determined by bending the strip with a free cooling surface thereof facing outward, the process comprising the steps of: ejecting a molten metal alloy through a nozzle; applying the ejected molten metal alloy to a surface of a rotating roll; allowing the applied molten metal alloy to be quenched by the roll surface to form an amorphous strip of the metal alloy, the strip being quenched at a cooling rate, determined at a free surface thereof, of 103° C./sec or more in a temperature range of from 500° C. to 200° C.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: December 14, 2004
    Assignee: Nippon Steel Corporation
    Inventors: Hiroaki Sakamoto, Toshio Yamada, Takashi Sato
  • Semiconductor integrated circuit and method of manufacturing of semiconductor integrated circuit
    Publication number: 20040165467
    Abstract: A semiconductor integrated circuit makes use of nonvolatile memory cells of a fuse circuit connected to a dedicated signal line without using a nonvolatile memory intended for general purpose use, which is connected to a common bus, in order to store control information for defect relief and the like of circuit modules. The reliability of storage of the control information is not limited to the performance of storage of information in the nonvolatile memory intended for general purpose use, and the reliability of storage of the control information can be easily enhanced. Since a second wiring used in the transfer of the control information is of a wiring dedicated for its transfer, it needs not perform switching between connections to circuit portions used for actual operations in the circuit modules and their control. A circuit configuration for delivering the control information can be simplified.
    Type: Application
    Filed: February 25, 2004
    Publication date: August 26, 2004
    Applicant: Renesas Technology Corporation
    Inventors: Toshio Sasaki, Toshio Yamada
  • Sense amplifier circuit
    Patent number: RE38647
    Abstract: In order to enhance the sensitivity of a sense amplifier circuit, each one of the transistor pair composing the sense amplifier circuit is formed by transistors connected parallel in an even number of stages, and therefore the sense amplifier circuit is made of transistor pair having an extremely balanced characteristic, cancelling the asymmetricity of current-voltage characteristic of the transistor pair to null.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: November 9, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Yamauchi, Toshio Yamada