Abstract: A novel multifunctional nano-probe interface is proposed for applications in neural stimulation and detecting. The nano-probe interface structure consists of a carbon nanotube coated with a thin isolation layer, a micro-electrode substrate array, and a controller IC for neural cell recording and stimulation. The micro-electrode substrate array contains wires connecting the carbon nanotube with the controller IC, as well as microfluidic channels for supplying neural tissues with essential nutrition and medicine. The carbon nanotube is disposed on the micro-electrode substrate array made by silicon, coated with a thin isolation layer around thereof, and employed as a nano-probe for neural recording and stimulation.

Abstract: An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

Abstract: An interconnection structure is provided. The interconnection structure includes a substrate, a conductive barrier layer, a dielectric layer and a carbon nanotube. A conductive region is disposed in the substrate. The conductive barrier layer is disposed over the conductive region and the conductive barrier layer includes iron, cobalt or nickel. The dielectric layer is disposed on the substrate. The carbon nanotube is disposed in the dielectric layer to electrically connect with the conductive barrier layer.

Abstract: A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises a substrate. A polyacrylonitrile (PAN) powder is dissolved in a solvent and the solvent is heated to form a PAN solution. The PAN solution is cooled down and the PAN solution is then formed on the substrate. The PAN solution is allowed to stand and the solvent in the PAN solution is then removed to form a PAN dielectric layer on the substrate. A patterned conductive layer is formed on the PAN dielectric layer.

Abstract: The present invention is directed to a structure of a gradient barrier layer. The gradient barrier with a composite structure of metal/metal salt of different composition/metal such as Ta/TaxN1?x/TaN/TaxN1?x/Ta (tantalum/tantalumx nitride1?x/tantalum nitride/tantalumx nitride1?x/tantalum) is proposed to replace the conventional barrier for copper metallization. The gradient barrier can be formed in a chemical vapor deposition (CVD) process or a multi-target physical vapor deposition (PVD) process. For CVD process, using the characteristics of well-controlled reaction gas injection, the ratio of tantalum (Ta) and nitrogen (N) can be modulated gradually to form the gradient barrier. For the multi-target PVD process, the gradient barrier is formed by depositing multi-layers of different composition TaxN1?x films. After subsequent thermal cycle processes such as metal alloy, the inter-layer diffusion occurs and a more smooth distribution of Ta and N is achieved for the gradient barrier.

Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.

Abstract: An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.

Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the dielectric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

Abstract: An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the dielectric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

Abstract: The present invention is directed to a structure of a gradient barrier layer. The gradient barrier with a composite structure of metal/metal salt of different composition/metal such as Ta/TaxN1−x/TaN/TaxN1−x/Ta (tantalum/tantalumx nitride1−x/tantalum nitride/tantalumx nitride1−x/tantalum) is proposed to replace the conventional barrier for copper metallization. The gradient barrier can be formed in a chemical vapor deposition (CVD) process or a multi-target physical vapor deposition (PVD) process. For CVD process, using the characteristics of well-controlled reaction gas injection, the ratio of tantalum (Ta) and nitrogen (N) can be modulated gradually to form the gradient barrier. For the multi-target PVD process, the gradient barrier is formed by depositing multi-layers of different composition TaxN1−x films.

Abstract: The present invention is directed to a structure of a gradient barrier layer. The gradient barrier with a composite structure of metal/metal salt of different composition/metal such as Ta/TaxNl−x/TaN/TaxNl−x/Ta (tantalum/tantalumx nitride1−x/tantalum nitride/tantalumx nitride1−x/tantalum) is proposed to replace the conventional barrier for copper metallization. The gradient barrier can be formed in a chemical vapor deposition (CVD) process or a multi-target physical vapor deposition (PVD) process. For CVD process, using the characteristics of well-controlled reaction gas injection, the ratio of tantalum (Ta) and nitrogen (N) can be modulated gradually to form the gradient barrier. For the multi-target PVD process, the gradient barrier is formed by depositing multi-layers of different composition TaxN1−x films.

Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.

Abstract: This invention relates to a structure of a dual damascene, in particular to a structure of a dual damascene using in a via. The structure of this dual damascene via comprises of; the first gap, the second gap, the third gap, a barrier layer, the first conductive layer, the second conductive layer, the first dielectric barrier cap, the second dielectric barrier cap, the first low dielectric constant (k) dielectric layer, and the second low dielectric constant dielectric layer. The structure of the present invention can obtain better electromigration (EM) resistance and better via resistance stability by using the third gap to be situated in the first conductive layer.

Abstract: A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.

Abstract: A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.