Abstract: The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-Si on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently.

Abstract: A semiconductor fabrication method is provided for the fabrication of a dual-damascene structure in an integrated circuit with a multilevel-interconnect structure. This method is characterized in that, after the dual-damascene hole is formed, a conformal barrier/adhesive layer is first formed over all the sidewalls of the dual-damascene hole, but not filling the dual-damascene hole. An anisotropic etching process is then performed to etch away the part of the conformal barrier/adhesive layer that is laid at the bottom of the dual-damascene hole and subsequently the underlying part of the topping layer until exposing the metallization layer. Finally, a conductive material, such as copper, is deposited into the remaining void portion of the dual-damascene hole. The deposited conductive material and the remaining part of the conformal barrier/adhesive layer in the dual-damascene hole in combination constitute the intended dual-damascene structure.

Abstract: A method for fabricating a shallow trench isolation. A pad oxide layer and a mask layer are formed over a substrate. The pad oxide layer, the mask layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A liner oxide layer is formed on the substrate exposed by the trench. An isolation layer is formed over the substrate to cover the liner oxide layer. The isolation layer is conformal to the trench. An oxide layer is formed over the substrate to fill the trench. A portion of the oxide layer and the isolation layer is removed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to form a shallow trench isolation.

Abstract: A method of fabricating a shallow trench isolation structure is described. A mask layer is formed on the substrate. The mask layer and the substrate are patterned to form trenches in the substrate. The trenches comprise a smallest trench. A first isolation layer is formed on the mask layer to fill partially the trenches. A densification step is performed. A second isolation layer is formed on the first isolation layer to fill completely the trench. The first isolation layer and the second isolation layer are removed until the mask layer is exposed. The mask layer is removed.

Abstract: A method for forming a poly gate structure is disclosed. The method comprises forming a dielectric layer on a substrate and then forming a polysilicon layer on the dielectric layer. A metal silicide layer is then formed on the polysilicon layer and, just after formation of metal silicide is accomplished completely, an annealing process is practiced to induce phase transformation of metal silicide layer. Afterwards, a passivation layer is formed over the metal silicide layer, and then a standard photolithography method is applied to form primary structure of poly gate. Finally, both gate etch anneal and sidewall rapid thermal oxidation are used to form the poly gate structure completely. The essential point of the method is that the metal silicide is annealed just when it is formed, such that there is no phase transition of metal silicide will occur while any further treatment of the poly gate. By the way, surface extrusion of poly gate is fundamental prevented.

Abstract: A method for forming a gate on a substrate for manufacturing semiconductor devices is described. The present method comprises the step of providing a gate oxide layer on top of a substrate. A polysilicon layer is overlaid on the gate oxide layer and then, a amorphous silicon layer is formed thereon. The stack of amorphous and polysilicon layers is defined to form a gate structure on gate oxide layer. Next, a thermal treatment is performed on the gate structure.

Abstract: A method for fabricating a gate structure. The method involves providing a substrate, followed by forming a nitride region on a surface of the substrate. With a Tantalum (Ta)-based organic compound and a Titanium (Ti)-based organic compound serving as precursors, an organic metal chemical vapor deposition (OMCVD) is performed, so that a Ta2−xTixO5 dielectric layer is formed on the substrate. A barrier layer, a conducting layer, and an anti-reflection (AR) layer are then formed in sequence on the Ta2−xTixO5 dielectric layer. Subsequently, the AR layer, the conducting layer, the barrier layer, and the Ta2−xTixO5 dielectric layer are defined to form a gate structure on the substrate of the nitride region. The Ta-based organic compound in this case may include a Ta-alkoxide compound, whereas the Ti-based organic compound may include a Ti-alkoxide compound or a Ti-amide compound.

Abstract: A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.

Abstract: A method for forming shallow trench isolation is disclosed. The method includes forming a trench in a semiconductor substrate, and then blanket depositing a silicon oxide layer over the semiconductor substrate by a plasma process, thereby substantially refilling the trench. Thereafter, a photoresist layer is formed on the plasma deposited silicon oxide layer, followed by etching back a portion of the photoresist layer. The plasma deposited silicon oxide layer is then isotropically etched, and the photoresist layer is then finally removed.

Abstract: A method of patterning a dielectric layer. On a substrate having a metal wiring layer formed thereon, a dielectric layer and a masking layer are formed. A cap insulation layer is formed on the masking layer before patterning the dielectric layer. In addition, a dual damasecence process is used for patterning the dielectric layer.

Abstract: A method of patterning a dielectric layer. On a substrate having a metal wiring layer formed thereon, a dielectric layer and a masking layer are formed. A cap insulation layer is formed on the masking layer before patterning the dielectric layer. In addition, a dual damasecence process is used for patterning the dielectric layer.

Abstract: A simplified method is disclosed for etching low k organic dielectric film. A substrate is provided with a hardmask layer and low k organic dielectric layer formed thereon in which hardmask layer is on the dielectric layer. A layer of photoresist is formed on the hardmask layer and imaged with a pattern by exposure through a dark field mask. As a key step, the pattern is transferred into the hardmask layer by dry etching and then the photoresist is stripped in-situ. Then, the interconnect is formed by using dry etching the low k organic dielectric layer using the hardmask layer as a mask, and readying it for the next semiconductor process.

Abstract: An improved method for forming shallow trench isolation structure is described. The present method comprises the steps of providing a pad oxide layer and a mask layer on a semiconductor substrate and forming a trench structure therein. Next, a liner oxide layer is formed on the surface of the trench structure in the semiconductor substrate and is extensively formed on the side surface of the mask layer exposed therein and the top surface of the mask layer by wet oxidation. A dielectric material is deposited on the liner oxide layer and fills the trench structure. The dielectric material layer is planarized. The mask layer and the pad oxide layer are then removed to form the isolation structures. The method for forming the shallow trench structures on a semiconductor structure in accordance with the present invention can eliminate the kink effect that occurs in the conventional method.

Abstract: An improved dual damascene process for forming metal interconnects comprising the steps of providing a semiconductor substrate that has a conductive layer, a first dielectric layer and a first mask layer already formed thereon. The first dielectric layer is made from a low-k dielectric material. A first silicon oxynitride (SiON) layer is formed over the first mask layer. Next, the first silicon oxynitride layer is patterned, and then the first mask layer is etched using the first silicon oxynitride as a mask. Subsequently, a second dielectric layer and a second mask layer are formed over the first silicon oxynitride. The second dielectric layer can be made from a low-k dielectric material. Next, a second silicon oxynitride layer is formed over the second mask layer. Thereafter, the second silicon oxynitride layer is patterned, and then the second mask layer is etched using the second silicon oxynitride layer as a mask.

Abstract: A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.

Abstract: The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-SI on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently.

Abstract: A method for fabricating a gate. A gate oxide layer is formed on a substrate. A first doped polysilicon layer is formed on the gate oxide layer. A second doped polysilicon layer on the first doped polysilicon layer. A third doped polysilicon layer over the second polysilicon layer. The second doped polysilicon layer has a grain size larger than a grain size of both the first doped polysilicon layer and the third dope polysilicon layer.

Abstract: A fabricating method of a capacitor includes two gates and a commonly used source/drain region formed on a substrate. Then, a process of sell align contact has been applied to make a pitted self align contact window (PSACW) to partly expose the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are formed over the PSACW. Then a dielectric thin film with a material having high dielectric constant is formed over the lower electrode. Then, an upper electrode is formed over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.

Abstract: A method for fabricating a semiconductor device. A substrate having a gate is provided. An ion implantation process is performed to form lightly doped source/drain region in the substrate. A liner layer and an insulation layer are formed over a substrate in sequence. A portion of the insulation layer is removed by an anisotropic etching process. The insulation layer remaining on sidewalls of the gate is used as a spacer. A top of the spacer is substantially level with an upper surface of the liner layer. An ion implantation process is performed to form heavily doped source/drain region in the substrate. A portion of the spacer is removed by wet etching. As a result, a top surface of the spacer is lower than the upper surface of the gate. The method can increase the exposed surface of the gate and maintain sufficient width of the lightly doped source/drain region to prevent the hot carrier effect and the short channel effect.

Abstract: A method of fabricating a dielectric layer for a dynamic random access memory capacitor is described in which a tantalum pentoxide layer is deposited on the polysilicon storage electrode, followed by a two-step treatment on the tantalum pentoxide layer. The first treatment step includes a remote oxygen plasma or an ultraviolet-ozone treatment, followed by a spike annealing second treatment step.