Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

Abstract: The present disclosure relates generally to gene delivery using a chimeric, retroviral-RNA replicon vector particle for increased expression of transgenes in a host cell. In particular, the chimeric vectors described herein can be used in any of a variety of settings including gene therapy and vaccine settings.

Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.

Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.

Abstract: A doorbell system includes a power supply circuit, a smart module, a chime, a chime switch and a control module. The smart module provides a smart function. The chime switch is electrically connected between the control module, the smart module, and the power supply circuit. When the chime switch is turned on, the current flows through the chime under control of the control module. When the chime switch is turned off, the current cannot flow through the chime under control of the control module; consequently, the buzzing sound cannot be generated.

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

Abstract: The present disclosure relates generally to gene delivery using a chimeric, retroviral-RNA replicon vector particle for increased expression of transgenes in a host cell. In particular, the chimeric vectors described herein can be used in any of a variety of settings including gene therapy and vaccine settings.

Abstract: A structure of semiconductor device is provided, including a substrate. A first trench isolation and a second trench isolation are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the germanium doped layer region.

Abstract: The present disclosure relates generally to gene delivery using a chimeric, retroviral-RNA replicon vector particle for increased expression of transgenes in a host cell. In particular, the chimeric vectors described herein can be used in any of a variety of settings including gene therapy and vaccine settings.

Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate and forming an isolation structure over the substrate. In addition, the fin structure is protruded from the isolation structure. The method further includes trimming the fin structure to a first width and forming a Ge-containing material covering the fin structure. The method further includes annealing the fin structure and the Ge-containing material to form a modified fin structure. The method also includes trimming the modified fin structure to a second width.

Abstract: A mattress, bed, cushion, or other device to support a user in a pre-determined posture. The mattress, bed, cushion, or other device includes compressible cells configured to inflate based on characteristics of particular contact areas of the user, and contact, in response to inflating based on the characteristics, the user in various contact areas to support the pre-determined posture. In particular, inflating the compressible cells based on characteristics of particular contact areas reduces the risk of the user developing pressure ulcers.

Abstract: An electronic device including a main body, a handle and a driven mechanism is provided. The main body includes a base and a button unit movably disposed on the base. The handle is movably connected to the main body. The handle is adapted to be rotated from a first position to a second position relative to the main body. The driven mechanism includes a first connection element and an ascending/descending assembly. A first section of the first connection element is fixed to the handle, and a second section of the first connection element is movably disposed in the base. The ascending/descending assembly is disposed in the base and located between the second section and a bottom of the button unit. When the handle is rotated from the first position to the second position, the first connection element moves with the handle, and the ascending/descending assembly is moved with the second section and lifts up the button unit.

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

Abstract: A mattress for patient care. The mattress includes a number of compressible cells and a number of sensors corresponding to the number of compressible cells. Each compressible cell is configured to contact, when inflated, a user in a contact area of a plurality of contact areas of the user. Each sensor is configured to generate a number of measurements, wherein each measurement relates to the contact area of a corresponding compressible cell. Each sensor is further configured to send the number of measurements to a pressure control device.

Abstract: A light source board includes a substrate; a metal reactive layer disposed on the substrate; a metal conductive layer disposed on the metal reactive layer; a metal alloy layer disposed on the metal conductive layer; and at least one light source disposed on the metal alloy layer. A material of the metal reactive layer is a Sn—Bi type alloy or a Sn—Ag—Cu type alloy, and arrangements of materials of the metal reactive layer and the metal conductive layer are respectively an arrangement of silver paste and copper, an arrangement of silver paste and nickel, an arrangement of silver paste and silver, an arrangement of copper paste and copper, an arrangement of copper paste and nickel, or an arrangement of copper paste and silver.

Abstract: An antifuse device is disclosed. The antifuse device includes a plurality of active regions, a plurality of word lines extending along a first direction and cut through the active regions, a plurality of bit lines and a plurality of source lines extending along a second direction and stride across the active regions. The bit lines and the source lines are arranged alternatively along the first direction. Plural antifuse capacitors are disposed along the source lines and connected between the source lines and the active regions.

Abstract: The present disclosure relates generally to gene delivery using a chimeric, retroviral-RNA replicon vector particle for increased expression of transgenes in a host cell. In particular, the chimeric vectors described herein can be used in any of a variety of settings including gene therapy and vaccine settings.

Abstract: A light source board includes a substrate, a composite circuit layer on the substrate, a first protective layer on the composite circuit layer, and a plurality of light sources on the pad portions, respectively. The substrate has a long side, a first short side, and a second short side. The composite circuit layer includes a first conductive trace layer and a second conductive trace layer stacked on the first conductive trace layer. A conductivity of the second conductive trace layer is higher than a conductivity of the first conductive trace layer. The composite circuit layer has a wire portion formed of at least the first conductive trace layer and a plurality of pad portions each formed of at least the first conductive trace layer and the second conductive trace layer. The wire portion is electrically coupled to the pad portions. The first protective layer exposes the pad portions.