Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.

Abstract: A method includes forming a fin protruding from a semiconductor substrate; forming a dummy gate stack over the fin, wherein forming the dummy gate stack includes depositing a layer of amorphous material over the fin; performing an anneal process on the layer of amorphous material, wherein the anneal process recrystallizes the layer of amorphous material into a layer of polycrystalline material, wherein the anneal process includes heating the layer of amorphous material for less than one millisecond; and patterning the layer of polycrystalline material; and forming an epitaxial source/drain region in the fin adjacent the dummy gate stack; and removing the dummy gate stack and replacing the dummy gate stack with a replacement gate stack.

Abstract: A doorbell system includes a power supply circuit, a smart module, a chime, a chime switch and a control module. The smart module provides a smart function. The chime switch is electrically connected between the control module, the smart module, and the power supply circuit. When the chime switch is turned on, the current flows through the chime under control of the control module. When the chime switch is turned off, the current cannot flow through the chime under control of the control module; consequently, the buzzing sound cannot be generated.

Abstract: In an embodiment, a device includes: a first semiconductor fin extending from a substrate; a second semiconductor fin extending from the substrate; a hybrid fin over the substrate, the second semiconductor fin disposed between the first semiconductor fin and the hybrid fin; a first isolation region between the first semiconductor fin and the second semiconductor fin; and a second isolation region between the second semiconductor fin and the hybrid fin, a top surface of the second isolation region disposed further from the substrate than a top surface of the first isolation region.

Abstract: A power supply method for a video doorbell is provided. The video doorbell is electrically connected with an external power supply unit. The video doorbell includes a camera unit, a power storage unit and an actuation unit. The power supply method includes the following steps. If the actuation unit is triggered, the power storage unit provides electric power to the camera unit. If the actuation unit has been triggered for a time duration longer than a predetermined length of time, the power supply unit provides electric power to the camera unit.

Abstract: In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.

Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region forms a semiconductor fin.

Abstract: A semiconductor device includes a substrate having a P-type device region and an N-type device region, wherein the P-type device region includes germanium dopants. A first gate oxide layer is formed on the P-type device region and a second gate oxide layer is formed on the N-type device region. The first gate oxide layer and the second gate oxide layer are formed through a same oxidation process. The first gate oxide layer includes nitrogen dopants and the second gate oxide layer does not include the nitrogen dopants.

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.

Abstract: The present disclosure relates generally to gene delivery using a chimeric, retroviral-RNA replicon vector particle for increased expression of transgenes in a host cell. In particular, the chimeric vectors described herein can be used in any of a variety of settings including gene therapy and vaccine settings.

Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.

Abstract: A doorbell system includes a power supply circuit, a smart module, a chime, a chime switch and a control module. The smart module provides a smart function. The chime switch is electrically connected between the control module, the smart module, and the power supply circuit. When the chime switch is turned on, the current flows through the chime under control of the control module. When the chime switch is turned off, the current cannot flow through the chime under control of the control module; consequently, the buzzing sound cannot be generated.

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

Abstract: The present disclosure relates generally to gene delivery using a chimeric, retroviral-RNA replicon vector particle for increased expression of transgenes in a host cell. In particular, the chimeric vectors described herein can be used in any of a variety of settings including gene therapy and vaccine settings.

Abstract: A structure of semiconductor device is provided, including a substrate. A first trench isolation and a second trench isolation are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the germanium doped layer region.

Abstract: The present disclosure relates generally to gene delivery using a chimeric, retroviral-RNA replicon vector particle for increased expression of transgenes in a host cell. In particular, the chimeric vectors described herein can be used in any of a variety of settings including gene therapy and vaccine settings.

Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.