Abstract: The invention provides a method and an apparatus that prevent the accumulation of copper ions during CMP of copper lines by performing the CMP process at low temperatures and by maintaining this low temperature during the CMP process by adding a slurry that functions as a corrosion inhibitor.

Abstract: A method for preventing a photo-induced chemical attack on a copper containing dielectric material including providing a copper or copper oxide containing dielectric material having an exposed copper containing surface; providing an acidic cleaning solution for contacting the exposed copper containing surface; and, shielding the exposed copper containing surface to substantially block incident light from impacting the exposed copper containing surface while contacting the exposed copper containing surface with the cleaning solution.

Abstract: A chemical mechanical polishing apparatus that is equipped with a chilled retaining ring and a method for using the apparatus are described. The retaining ring is mounted therein a heat transfer means such as a metal tube and flowing therethrough a heat exchanging fluid for carrying away heat from the wafer mounted in the retaining ring, resulting in a temperature reduction in the slurry solution that contacts the wafer. The present invention apparatus and method therefore reduces the delamination problem for low k dielectric materials during polishing and the wafer scratching problem.

Abstract: A method for forming a protective oxide liner to reduce a surface reflectance including providing a hydrophilic insulating layer over a conductive layer; providing an anti-reflectance coating (ARC) layer over the hydrophilic insulating layer; providing an etching stop layer over the anti-reflectance coating (ARC) layer; photolithographically defining a pattern on a surface of the etching stop layer for etching; anisotropically etching at least one etch opening extending at least partially through a thickness of the hydrophilic insulating layer; depositing an oxide liner such that the sidewalls and bottom portion of the at least one etch opening and said surface are covered by the oxide liner; and, removing the oxide liner from aid surface according to a chemical mechanical (CMP) process to a surface reflectance.

Abstract: A method for forming a metal filled semiconductor feature including a low dielectric constant CMP polishing stop layer for improving a CMP polishing process including providing a semiconductor processing surface having a anisotropically etched semiconductor feature formed through a thickness including a second dielectric insulating layer overlying a first dielectric insulating layer, the second dielectric insulating layer having a CMP material removal rate in a CMP process less than about ½ of a CMP material removal rate of the first dielectric insulating layer in the CMP process; filling the anisotropically etched semiconductor feature with a metal to form a metal filled semiconductor feature; and, planarizing according to the CMP process excess material including the metal overlying the second dielectric insulating layer.

Abstract: The invention teaches a new method of applying slurry during the process of chemical mechanical polishing of copper surfaces. By varying the rate of slurry deposition, starting out with a low rate of slurry flow that is increased as the polishing process proceeds, the invention obtains good planarity for copper surfaces while saving on the amount of slurry that is being used for the copper surface polishing process.

Abstract: A method for avoiding a step height over an alignment mark area including providing at least one alignment mark area disposed at a semiconductor wafer process surface periphery said alignment mark area having alignment marks anisotropically etched into the semiconductor wafer process surface; depositing a first insulating dielectric layer over an active area of the semiconductor wafer process surface to include covering the at least one alignment mark area; planarizing the first insulating dielectric layer; depositing a polysilicon layer over the active area of the semiconductor wafer process surface to include covering the at least one alignment mark area; and, anisotropically etching the polysilicon layer through a thickness over the at least one alignment mark area to form an opening extending no further than about the first insulating dielectric layer to minimize a step height.

Abstract: A method of copper metallization wherein copper flaking and metal bridging problems are eliminated by an annealing process is described. A first metal line is provided on an insulating layer overlying a semiconductor substrate. A dielectric stop layer is deposited overlying the first metal line. A dielectric layer is deposited overlying the dielectric stop layer. An opening is etched through the dielectric layer and the dielectric stop layer to the first metal line. A barrier metal layer is deposited over the surface of the dielectric layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and barrier metal layer not within the opening are polished away wherein after a time period, copper flakes form on the surface of the copper and dielectric layers.

Abstract: A method is presented for forming a protective oxide liner including providing an insulating layer over a conductive layer; providing an anti-reflectance layer over the insulating layer; providing an etching stop layer over the anti-reflectance layer; photolithographically defining a pattern on a surface of the etching stop layer for etching; anisotropically etching at least one etch opening extending at least partially through a thickness of the insulating layer; depositing an oxide liner such that the sidewalls of the at least one etch opening and said surface are covered by the oxide liner; and, removing the oxide liner from said surface.

Abstract: A process for forming a dual damascene opening, in a composite layer comprised with low k layers, to accommodate a dual damascene type, copper structure, has been developed. The process features the use of a silicon oxide layer, formed on the surfaces of the composite layer, exposed in the narrow diameter, via hole component of the dual damascene opening. The silicon oxide layer prevents via poisoning, or outgassing of amines or hydroxyls from the low k layers exposed in the via hole opening, that can evolve during a subsequent photolithographic development cycle, used to define the trench shape component of the dual damascene opening. The protective silicon oxide layer is conformally formed on the exposed-surfaces of the via hole component, via a liquid phase deposition procedure, performed at room temperature.

Abstract: Reducing metal corrosion, such as copper corrosion, in semiconductor devices, is disclosed. A semiconductor device includes an insulating layer, a metal line, one or more corrosive metal components, and one or more sacrificial corrosive metal components. The metal line is situated within the insulating layer. The one or more corrosive metal components are situated within the insulating layer and connected to the metal line. The one or more sacrificial corrosive metal components are situated within the insulating layer and connected to the metal line. The presence of the sacrificial components substantially reduces corrosion of the non-sacrificial components.

Abstract: A continuous loop polishing pad that is reinforced by a reinforcing filler and a method for fabricating the polishing pad are described. The reinforced polishing pad is constructed by a sub-layer and a top layer, wherein the sub-layer defines an inner diameter of the polishing pad and contains a reinforcing filler with an aspect ratio of at least 10 oriented substantially in a circumferential direction of the continuous loop polishing pad. The top layer is laminated to the sub-layer with a top surface defining an outer diameter of the polishing pad, while both the sub-layer and the top layer are formed of a polymeric material. The invention further describes a method for fabricating the reinforced polishing pad in a continuous loop.

Abstract: A bond pad structure that is supported by a multiplicity of vias arranged in at least two regions each having a different via density than the other and a method for forming the structure are described. The structure includes a layer of an insulating material such as a low-k dielectric, a first multiplicity of vias formed in a center region of the low-k dielectric material that has a first density, a second multiplicity of vias formed in a peripheral region of the low-k dielectric material surrounding the center region that has a second density, wherein the second density is higher than the first density. A conductive metal pad of generally rectangular shape is then formed on top of and electrically connected to the first and second multiplicity of vias.

Abstract: A process for creating a copper damascene structure, totally encapsulated with conductive barrier shapes, has been developed. After formation of a copper damascene structure, encased with tantalum or tantalum nitride barrier shapes, coating the bottom and sides of the copper damascene structure, another conductive barrier shape, is formed on the top surface of the copper damascene structure. This conductive barrier shape, located on the top surface of the copper damascene structure, is formed via patterning of a blanket conductive barrier layer, via an anisotropic RIE procedure, using a photoresist shape as an etch mask. The photoresist shape in turn, is formed in negative photoresist layer, using the same photolithographic exposure plate, previously used to define the opening in the insulator layer, in which the copper damascene structure resides.

Abstract: A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

Abstract: A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a dielectric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.

Abstract: A polishing pad platen that is equipped with a guard ring, or a slurry retaining collar, used in chemical mechanical polishing (CMP) for conserving usage of polishing slurry is described. A method for conserving slurry solution during a CMP process is further described. In the novel polishing pad platen, a guard ring is mounted to the platen by sealiningly engaging an outer periphery of the platen for preventing spilling out of slurry solution during a polishing operation. The guard ring is mounted to slidingly engage the platen in such a way that the ring may be lowered to be completely out of the way during a pad condition process in which the spinning out of a pad conditioning solution from a top surface of the polishing pad is necessary.

Abstract: Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

Abstract: An improved and new process, used for the elimination of copper line damage in damacene processing, is disclosed. By depositing copper by physical vapor deposition (PVD), sputtering, preferably by an ion metal plasma (IMP) scheme or chemical vapor deposition (CVD), the deposited copper fills pinholes or intra-cracks (micro-cracks), caused by poor gap filling of purely electrochemical deposition of copper plating. By this process or method, chemical attack on copper lines, by chemicals in the subsequent chemical mechanical polish (CMP) back and post-cleaning steps, is prevented.

Abstract: A process for reducing dishing in damascene structures formed in low k organic dielectrics is described. A key feature is the insertion of a liner layer between the low k dielectric layer and the etch stop layer. The only requirement for the liner material is that it should have different etching characteristics from the etch stop material so that when trenches are etched in the dielectric they extend as far as the etch stop layer, in the normal way. When this is done it is found that dishing, after CMP, is significantly reduced, particularly for trench structures made up of multiple narrow trenches spaced close together.