Abstract: A composite, dual-hardness polishing pad for use in a linear chemical mechanical polishing apparatus and a method for forming the pad are described. In the composite, dual-hardness polishing pad, a pad body is first provided which has a leading edge and a trailing edge for mounting to a linear belt immediately adjacent to a second polishing pad. The pad body is fabricated of a material that has a first hardness, the leading edge contacts an object being polished on the composite polishing pad before the trailing edge when the linear belt turns in a linear polishing process. The composite polishing pad further includes a buffer pad that is adhesively joined to the leading edge of the pad body for contacting the object that is being polished, the buffer pad may be fabricated of a material that has a second hardness which is at least 20% smaller than the first hardness such that impact on the object being polished is minimized during a linear polishing process.

Abstract: A slurry dispensing unit for a chemical mechanical polishing apparatus equipped with multiple slurry dispensing nozzles is disclosed. The slurry dispensing unit is constructed by a dispenser body that has a delivery conduit, a return conduit and a U-shape conduit connected in fluid communication therein between for flowing continuously a slurry solution therethrough and a plurality of nozzles integrally connected to and in fluid communication with a fluid passageway in the delivery conduit for dispensing a slurry solution. The multiple slurry dispensing nozzles may either have a fixed opening or adjustable openings by utilizing a flow control valve at each nozzle opening.

Abstract: The invention provides a method and an apparatus that prevent the accumulation of copper ions during CMP of copper lines by performing the CMP process at low temperatures and by maintaining this low temperature during the CMP process by adding a slurry that functions as a corrosion inhibitor.

Abstract: A process for manufacturing damascene wiring in integrated circuits is described. Trenches in the top most layer are first over-filled with a soft metal (such as copper) and then a relatively thin layer of a hard material such as tantalum, tantalum nitride, titanium, titanium nitride etc is deposited on the copper surface Under a first set of control conditions CMP is then applied for just long enough to selectively remove this hard material layer from peaks in the copper surface while leaving it intact in the valleys. The control conditions for CMP are then adjusted so that CMP can proceed with material at the peaks being removed at a significantly faster rate than in the valleys. Thus, when the point is reached that all copper outside the trenches has been removed, the trenches are found to be just filled with a flat layer that has no dishing.

Abstract: Chemical mechanical polishing (CMP) is known to cause dishing when the surface being planarized includes a wide trench partially filled with metal. This problem has been overcome by first filling the trench with a material whose polishing rate under CMP is similar to that of the metal in the trench. Spin-coating is used for this so that only the trench gets filled. After CMP, any residue of this material is removed, leaving behind a surface that has been planarized to the intended extent without the introduction of significant dishing and with minimum erosion of the metal.

Abstract: A new method is provided that affects the polishing rate of the surface of a layer of copper, that has been deposited over the surface of a layer of dielectric. Copper damascene structures have been created in the surface of the layer of dielectric, the layer of dielectric also overlies an alignment mark. The surface of the layer of dielectric that is aligned with the alignment mark is provided with dummy damascene structures, assuring equal polishing rates for active damascene structures and the surface region of the layer of dielectric overlying an alignment mark.

Abstract: A method of forming a planarized metal interconnect comprising the following steps. A semiconductor structure is provided. A low K dielectric layer is formed over the semiconductor structure. A sacrificial layer over is formed over the low K dielectric layer. The sacrificial layer and low K dielectric layer are patterned to form a trench within the sacrificial layer and low K dielectric layer. A barrier layer is formed over the sacrificial layer, lining the trench side walls and bottom. Metal is deposited on the barrier layer to form a metal layer filling the lined trench and blanket filling the sacrificial layer covered low K dielectric layer. The metal layer and the barrier layer are planarized, exposing the upper surface of the sacrificial layer. The sacrificial layer is removed to form a planarized metal interconnect.

Abstract: A new method is provided to create aluminum pads that overlay an electrical contact point. A thick layer of passivation is deposited over the surface that contains one or more electrical contact points, the layer of passivation is patterned thereby creating openings in the layer of passivation that overlay and align with one or more of the contact points. A layer of aluminum is sputter deposited over the passivation layer including the openings that has been created in the passivation layer, this layer of aluminum is sputtered to a thickness such that the surface of the aluminum that is created in the openings in the layer of passivation is lower than the surface of the layer of passivation. The deposited layer of aluminum is polished using methods of CMP whereby the polishing end point is the surface of the layer of passivation.

Abstract: The invention provides a method and an apparatus that prevent the accumulation of copper ions during CMP of copper lines by performing the CMP process at low temperatures and by maintaining this low temperature during the CMP process by adding a slurry that functions as a corrosion inhibitor.

Abstract: A new method is provided for the alignment of the patterning of AlCu pads in an environment of copper interconnect line patterns. A layer of passivation material is deposited over a surface that contains alignment marks. The layer of passivation is patterned creating in the surface of the layer of passivation the opening that is required for the AlCu pad in addition to openings for a new pattern of alignment marks. A layer of AlCu is sputter deposited over the surface of the layer of passivation thereby including the openings that have been created in the layer of passivation. This creates a new pattern of alignment marks in the surface of the deposited layer of AlCu whereby these new alignment marks align with the pattern of new alignment marks that has been etched in the layer of passivation. The new alignment marks are then used to pattern the layer of AlCu for the creation of the AlCu pad.

Abstract: A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a dielectric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.

Abstract: A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a di electric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.

Abstract: An apparatus and a method for chemical mechanical polishing a metal on a semiconductor wafer capable of achieving improved pad life are disclosed. In the apparatus, in addition to a first spray nozzle used for spraying a slurry solution onto the top of a polishing pad, a second spray nozzle is provided for mounting juxtaposed to a conditioning pad for dispensing a cleaning solution capable of dissolving polishing debris formed on the polishing pad surface. The apparatus may further include at least one cleaning solution reservoir for storing and delivering a cleaning solution to the second spray nozzle. The method can be advantageously carried out in two-steps during which a first cleaning solution is sprayed onto the pad surface for dissolving the polishing debris, and then a second cleaning solution is sprayed onto the pad surface for removing or flushing away the dissolved debris.

Abstract: An Integrated Circuit Design which adds, to the standard conducting lines of the bulk metal layer, a pattern of a support structure which supports subsequent deposition in such a way that it eliminates previously experienced concavity or dishing of the subsequent deposition within areas which have a low density or absence of conducting lines. The dummy pattern enhances the deposition of filler material between conducting lines of the Integrated Circuit such that planarization of the bulk metal results in a smoother surface of the areas of the signal lines of the integrated circuit and within large open areas. Concurrently the present invention provides a means of successfully collecting data that are needed for Damascene processing.

Abstract: A new method for removing particle residue from the surface of semiconductor wafers that contain wolfram plugs. A series of polishing and buffing steps is performed; the first of this is a wolfram CMP using a hard polishing pad. An oxide buffing operation is further performed on the wafer surface; a soft pad is used for this buffing operation. The buffing operation is followed by a wolfram CMP that is applied for a short period of time using a soft polishing pad thereby removing the protruding top of the wolfram plug and the oxide particles from the vicinity of the wolfram plugs.

Abstract: An improvement in the box-in-box overlay measurement method has been achieved by forming the outer box from a segmented trench comprised of a number of concentric ridges that project upwards from the floor of the trench. When the segmented trench has been overfilled with tungsten (or similar metal) the excess metal is removed using either etch-back or chem. mech. polishing as the planarizing technique. Because of the presence of the ridges, the trench (i.e. the outer box) becomes reproducibly easy to see when the inner box (which will be etched from a second layer deposited on the first one) is being positioned inside it. Furthermore, the tendency for the outer box to be broken in critical places (often seen in the prior art) is now largely eliminated.

Abstract: A method for forming a copper structure with reduced dishing, using a self-aligned copper electroplating process. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer has a trench therein. A barrier layer is formed over the dielectric layer, a seed layer is formed on the barrier layer, and an insulating layer is formed on the seed layer. The insulating layer is patterned so as to expose the seed layer on the bottom and sidewalls of the trench, preferably using the trench photo mask. A copper layer is selectively electroplated onto the exposed seed layer on the bottom and sidewalls of the trench, while the insulating layer prevents copper deposition outside of the trench. The copper layer, the insulating layer, and the seed layer are planarized, stopping at the dielectric layer. Because of the self-aligned copper geometry, the copper suffers reduced dishing.

Abstract: This invention describes a method of forming alignment marks which will be preserved after contact holes in a dielectric have been filled with barrier metal and contact metal and the wafer has been planarized. The alignment marks are formed by filling alignment lines, formed in the dielectric when the contact holes are formed, with barrier metal and contact metal. The alignment lines and contact holes are filled with metal at the same time. After the wafer has been planarized, using a method such as chemical mechanical polishing, a small thickness of the dielectric is etched back using vertical dry anisotropic etching which will not remove either the contact metal or barrier metal. This leaves barrier metal and contact metal extending above the plane of the dielectric forming alignment marks. These alignment marks are preserved after subsequent processing steps, such as deposition of a layer of electrode metal.

Abstract: A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

Abstract: Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.