Patents by Inventor Tsuneo Ogura
Tsuneo Ogura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170263714Abstract: A semiconductor device includes first and second electrodes spaced apart along a first direction, a first semiconductor region of a first conductivity type between the first and second electrodes, first and second conductive regions between the first semiconductor region and the second electrode and electrically connected to the second electrode, a third electrode between the first and second conductive regions, second and third semiconductor regions of a second conductivity type respectively between the first and second conductive regions and the third electrode, and fourth and fifth semiconductor regions of the first conductivity type respectively between the second and third semiconductor regions and the second electrode. The third electrode extends in the first direction toward the first electrode farther than portions of the second and third semiconductor regions that are alongside the third electrode.Type: ApplicationFiled: August 29, 2016Publication date: September 14, 2017Inventors: Tsuneo OGURA, Tomoko MATSUDAI
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Patent number: 9741872Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first semiconductor region and the second electrode. The third semiconductor region is provided between the first semiconductor region and the second electrode, is provided beside the second semiconductor region in a second direction crossing a first direction from the first electrode toward the second electrode, and a portion of the first semiconductor region is positioned between the third and second semiconductor regions. The fourth semiconductor region is provided between the portion of the first semiconductor region and the second electrode and has a greater impurity concentration than the second and third semiconductor regions.Type: GrantFiled: September 4, 2015Date of Patent: August 22, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Tomoko Matsudai
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Publication number: 20170186884Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.Type: ApplicationFiled: March 16, 2017Publication date: June 29, 2017Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
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Patent number: 9634128Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.Type: GrantFiled: July 6, 2015Date of Patent: April 25, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
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Patent number: 9620631Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer.Type: GrantFiled: March 18, 2013Date of Patent: April 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoko Matsudai, Tsuneo Ogura, Yuichi Oshino, Hideaki Ninomiya, Kazutoshi Nakamura
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Patent number: 9613951Abstract: According to one embodiment, a semiconductor device includes a first and second electrode, a first, second, third and fourth semiconductor region, and a first intermediate metal film. The first region is provided above the first electrode and has a first impurity concentration. The second region is provided above the first region and has a second impurity concentration lower than the first impurity concentration. The third region is provided above the second region and has a third impurity concentration. The fourth region is provided above the second region and has a fourth impurity concentration lower than the third impurity concentration. The second electrode is provided above the third region and the fourth region and is in ohmic contact with the third region. The intermediate metal film is provided between the second electrode and the fourth region. The intermediate metal film forms Schottky junction with the fourth region.Type: GrantFiled: March 6, 2014Date of Patent: April 4, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tomoko Matsudai, Tsuneo Ogura, Yuuichi Oshino
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Publication number: 20170077089Abstract: According to one embodiment, in a semiconductor device, The first semiconductor region is provided between the first and the second electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The first and second connection region are electrically connected to the second electrode, reaches the first semiconductor region. The first insulating film is provided between the first connection region and the second semiconductor region and between the first connection region and the first semiconductor region. The second insulating film is provided between the second connection region and the second semiconductor region and between the second connection region and the first semiconductor region.Type: ApplicationFiled: February 18, 2016Publication date: March 16, 2017Inventors: Tsuneo Ogura, Tomoko Matsudai
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Patent number: 9496352Abstract: According to one embodiment, a semiconductor device includes: a first semiconductor region; a second semiconductor region on the first semiconductor region; a third semiconductor region on the second semiconductor region; an fourth insulating film on the second semiconductor region and the third semiconductor region; a first electrode under the first semiconductor region; a second electrode on the fourth insulating film; a plurality of first contact regions extending in a first direction from the first electrode toward the second electrode in the fourth insulating film, and the plurality of first contact regions electrically connecting the third semiconductor region to the second electrode; a plurality of second contact regions extending in the first direction in the fourth insulating film, and one of the plurality of second contact regions between adjacent ones of the first contact regions; and a third electrode in the second semiconductor region via a first insulating film.Type: GrantFiled: September 2, 2015Date of Patent: November 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Tomoko Matsudai, Norio Yasuhara, Tsuneo Ogura
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Publication number: 20160276444Abstract: According to one embodiment, a semiconductor device includes: a first semiconductor region; a second semiconductor region on the first semiconductor region; a third semiconductor region on the second semiconductor region; an fourth insulating film on the second semiconductor region and the third semiconductor region; a first electrode under the first semiconductor region; a second electrode on the fourth insulating film; a plurality of first contact regions extending in a first direction from the first electrode toward the second electrode in the fourth insulating film, and the plurality of first contact regions electrically connecting the third semiconductor region to the second electrode; a plurality of second contact regions extending in the first direction in the fourth insulating film, and one of the plurality of second contact regions between adjacent ones of the first contact regions; and a third electrode in the second semiconductor region via a first insulating film.Type: ApplicationFiled: September 2, 2015Publication date: September 22, 2016Inventors: Tomoko Matsudai, Norio Yasuhara, Tsuneo Ogura
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Publication number: 20160276498Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first semiconductor region and the second electrode. The third semiconductor region is provided between the first semiconductor region and the second electrode, is provided beside the second semiconductor region in a second direction crossing a first direction from the first electrode toward the second electrode, and a portion of the first semiconductor region is positioned between the third and second semiconductor regions. The fourth semiconductor region is provided between the portion of the first semiconductor region and the second electrode and has a greater impurity concentration than the second and third semiconductor regions.Type: ApplicationFiled: September 4, 2015Publication date: September 22, 2016Inventors: Tsuneo Ogura, Tomoko Matsudai
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Patent number: 9391070Abstract: A semiconductor device includes first electrode, first semiconductor layer of first conductivity type on the first electrode, second semiconductor layer of second conductivity type on the first semiconductor layer, third semiconductor layer of the first conductivity type on second semiconductor layer, fourth semiconductor layer of the second conductivity type selectively located on the third semiconductor layer, gate electrode through the third and fourth semiconductor layers and into the second semiconductor layer and insulated therefrom, second electrode on the fourth semiconductor layer, fifth semiconductor layer of the second conductivity type between the first electrode and the second semiconductor layer, sixth semiconductor layer of the first conductivity type on the second semiconductor layer contacting the second electrode, and seventh semiconductor layer of the first conductivity type in the second and sixth semiconductor layers, such that the bottom thereof is closer to the first electrode than theType: GrantFiled: February 26, 2015Date of Patent: July 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoko Matsudai, Tsuneo Ogura, Bungo Tanaka
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Patent number: 9362359Abstract: A semiconductor device in an embodiment includes a first region of a second conductivity type between a first electrode and a second electrode and a second region of a first conductivity type between the first region and the second electrode. a third region of the second conductivity type is between the second region and the second electrode. A fourth and fifth region of the first conductivity type are between the third semiconductor region and the second electrode. The fourth and fifth regions are adjacent to each other. A dopant concentration in the fifth region is less than a dopant concentration in the fourth region. A third electrode contacts the second region, the third region, the fourth region, and the fifth region via an insulating film.Type: GrantFiled: July 10, 2014Date of Patent: June 7, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Tomoko Matsudai
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Patent number: 9337189Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.Type: GrantFiled: May 11, 2015Date of Patent: May 10, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
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Patent number: 9324815Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.Type: GrantFiled: May 1, 2015Date of Patent: April 26, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo Ogura, Tomoko Matsudai, Yuuichi Oshino, Yoshiko Ikeda, Kazutoshi Nakamura, Ryohei Gejo
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Patent number: 9318588Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.Type: GrantFiled: August 5, 2015Date of Patent: April 19, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Takuma Hara, Kazutoshi Nakamura, Tsuneo Ogura
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Patent number: 9293548Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity-type base layer, a second conductivity-type base layer, a second semiconductor layer, a buried layer, a buried electrode, a gate insulating film, a gate electrode, and a second major electrode. The buried layer of the second conductivity type selectively is provided in the first conductivity-type base layer. The buried electrode is provided in a bottom portion of a trench which penetrates the second conductivity-type base layer to reach the buried layer. The buried electrode is in contact with the buried layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer and the buried electrode.Type: GrantFiled: April 13, 2015Date of Patent: March 22, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Tsuneo Ogura
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Publication number: 20160079235Abstract: A semiconductor device includes first electrode, first semiconductor layer of first conductivity type on the first electrode, second semiconductor layer of second conductivity type on the first semiconductor layer, third semiconductor layer of the first conductivity type on second semiconductor layer, fourth semiconductor layer of the second conductivity type selectively located on the third semiconductor layer, gate electrode through the third and fourth semiconductor layers and into the second semiconductor layer and insulated therefrom, second electrode on the fourth semiconductor layer, fifth semiconductor layer of the second conductivity type between the first electrode and the second semiconductor layer, sixth semiconductor layer of the first conductivity type on the second semiconductor layer contacting the second electrode, and seventh semiconductor layer of the first conductivity type in the second and sixth semiconductor layers, such that the bottom thereof is closer to the first electrode than theType: ApplicationFiled: February 26, 2015Publication date: March 17, 2016Inventors: Tomoko MATSUDAI, Tsuneo Ogura, Bungo Tanaka
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Publication number: 20160079369Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, and a first semiconductor region provided between the first and second electrodes. A first element region includes a second semiconductor region provided between the first semiconductor region and the first electrode, a third semiconductor region provided between the first semiconductor region and the second electrode, a fourth semiconductor region provided between the third semiconductor region and the second electrode, and a third electrode provided in the first, third and fourth semiconductor regions. A second element region includes a fifth semiconductor region provided between the first semiconductor region and the first electrode, and a sixth semiconductor region provided between the first semiconductor region and the second electrode. An isolation region includes a seventh semiconductor region provided between the first semiconductor region and the second electrode.Type: ApplicationFiled: September 2, 2015Publication date: March 17, 2016Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai
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Publication number: 20160035869Abstract: A semiconductor device formed on a substrate of a first conductivity type, including a base layer of a second conductivity disposed on a first face of the substrate, an anode layer with a higher dopant amount in a portion of the base layer, an IGBT region formed on the base layer, a diode region formed on the anode layer, a trench extending from the top of the IGBT and diode regions in to the substrate. The area occupied by the diode region is different from the area occupied by the IGBT region, but they share collector and emitter electrodes. The contact area between the diode anode layer and the emitter electrode may be adjusted by the arrangement of trenches.Type: ApplicationFiled: July 30, 2015Publication date: February 4, 2016Inventors: Tomoko MATSUDAI, Tsuneo OGURA
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Publication number: 20150380535Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, and a gate electrode. The length in a first direction of a portion of the gate electrode opposing the third semiconductor region being longer than a length in the first direction of a portion of the gate electrode opposing the fifth semiconductor region. An impurity concentration of the second conductivity type of the fourth semiconductor region is higher than an impurity concentration of the second conductivity type of an intermediate portion in the third semiconductor region. At least a part of the intermediate portion is arranged with a part of the first insulating region in the third direction. At least a part of the fifth semiconductor region is not arranged with the first insulating region in the third direction.Type: ApplicationFiled: March 5, 2015Publication date: December 31, 2015Inventors: Yuuichi Oshino, Tsuneo Ogura