Patents by Inventor Tsuneo Ogura

Tsuneo Ogura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9224844
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor layer, a first semiconductor region, a second semiconductor region, and an insulating layer. The first semiconductor layer is provided between the first electrode and the second electrode, and contacts the first electrode. The first semiconductor region is provided between the first semiconductor layer and the second electrode, and contacts the second electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode, and contacts the second electrode. An impurity concentration of the second semiconductor region is higher than an impurity concentration of the first semiconductor region. An insulating layer has one end contacting the second electrode and the other end positioned in the first semiconductor layer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: December 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Tomoko Matsudai
  • Patent number: 9219060
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, third, fourth, fifth, sixth, and seventh semiconductor regions. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first electrode and the first semiconductor region. The third and fourth semiconductor regions are provided between the first electrode and the second semiconductor region. The fifth semiconductor region is positioned between the third semiconductor region and the second electrode, and is provided between the first semiconductor region and the second electrode. The sixth semiconductor region is positioned between the fourth semiconductor region and the second electrode, and is provided between the first semiconductor region and the second electrode. The seventh semiconductor region is provided between the fifth semiconductor region and the second electrode.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: December 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Ogura
  • Patent number: 9214535
    Abstract: A collector layer of a first conductivity type is provided in the IGBT region and the boundary region and functions as a collector of the IGBT in the IGBT region. A cathode layer of a second conductivity type is provided in the diode region apart from the collector layer and functions as a cathode of the diode. A drift layer of the second conductivity type is provided in the IGBT region, the boundary region, and the diode region, the drift layer being provided on sides of the collector layer and the cathode layer opposite the first electrode. A diffusion layer of the first conductivity type is provided in the boundary region on a side of the drift layer opposite the first electrode.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: December 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Matsudai, Tsuneo Ogura, Kazutoshi Nakamura, Yuichi Oshino, Hideaki Ninomiya, Yoshiko Ikeda
  • Publication number: 20150340478
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.
    Type: Application
    Filed: August 5, 2015
    Publication date: November 26, 2015
    Inventors: Takuma Hara, Kazutoshi Nakamura, Tsuneo Ogura
  • Publication number: 20150311326
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.
    Type: Application
    Filed: July 6, 2015
    Publication date: October 29, 2015
    Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
  • Patent number: 9159722
    Abstract: A semiconductor device includes a transistor region and diode region. A plurality of transistors is in the transistor region and at least one diode is in the diode region. The transistors include first and second body regions of a first conductivity type. The dopant concentration in the second body region is greater than the dopant concentration in the first body region. The diode includes first and second anode regions of the first conductivity type. The dopant concentration in the second anode region is greater than the dopant concentration in the first anode region. A total dopant amount in the second body region within a first block portion of the semiconductor substrate is greater than a total dopant amount in the second anode layer within a second block portion of the semiconductor substrate of the same size as the first block portion.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: October 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Shinichiro Misu, Ryohei Gejo, Norio Yasuhara
  • Publication number: 20150262999
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, third, fourth, fifth, sixth, and seventh semiconductor regions. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first electrode and the first semiconductor region. The third and fourth semiconductor regions are provided between the first electrode and the second semiconductor region. The fifth semiconductor region is positioned between the third semiconductor region and the second electrode, and is provided between the first semiconductor region and the second electrode. The sixth semiconductor region is positioned between the fourth semiconductor region and the second electrode, and is provided between the first semiconductor region and the second electrode. The seventh semiconductor region is provided between the fifth semiconductor region and the second electrode.
    Type: Application
    Filed: September 11, 2014
    Publication date: September 17, 2015
    Inventor: Tsuneo Ogura
  • Publication number: 20150263146
    Abstract: A semiconductor device in an embodiment includes a first region of a second conductivity type between a first electrode and a second electrode and a second region of a first conductivity type between the first region and the second electrode. a third region of the second conductivity type is between the second region and the second electrode. A fourth and fifth region of the first conductivity type are between the third semiconductor region and the second electrode. The fourth and fifth regions are adjacent to each other. A dopant concentration in the fifth region is less than a dopant concentration in the fourth region. A third electrode contacts the second region, the third region, the fourth region, and the fifth region via an insulating film.
    Type: Application
    Filed: July 10, 2014
    Publication date: September 17, 2015
    Inventors: Tsuneo OGURA, Tomoko MATSUDAI
  • Publication number: 20150263148
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor layer, a first semiconductor region, a second semiconductor region, and an insulating layer. The first semiconductor layer is provided between the first electrode and the second electrode, and contacts the first electrode. The first semiconductor region is provided between the first semiconductor layer and the second electrode, and contacts the second electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode, and contacts the second electrode. An impurity concentration of the second semiconductor region is higher than an impurity concentration of the first semiconductor region. An insulating layer has one end contacting the second electrode and the other end positioned in the first semiconductor layer.
    Type: Application
    Filed: September 11, 2014
    Publication date: September 17, 2015
    Inventors: Tsuneo Ogura, Tomoko Matsudai
  • Publication number: 20150263144
    Abstract: According to one embodiment, an insulated gate bipolar transistor includes a main region, a sense region, and a semiconductor layer that is provided between the main region and the sense region, is in contact with a collector layer of a first conductivity type provided in the main region and the sense region, and has one of a dopant concentration lower than a dopant concentration of the collector layer or a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: September 2, 2014
    Publication date: September 17, 2015
    Inventors: Shinichiro MISU, Tsuneo OGURA
  • Publication number: 20150263149
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, an insulating region, and a third semiconductor region. The first semiconductor region is of a first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and contacts the first electrode. The second semiconductor region is of a second conductivity type. The second conductor region is provided between the first semiconductor region and the second electrode. The insulating region extends from the second electrode to a side of the first semiconductor region. The third semiconductor region is of the first conductivity type. The third semiconductor region is provided in at least a portion of a region between the second semiconductor region and the insulating region, and contacts the first semiconductor region.
    Type: Application
    Filed: September 12, 2014
    Publication date: September 17, 2015
    Inventors: Tsuneo Ogura, Shinichiro Misu, Tomoko Matsudai, Norio Yasuhara
  • Publication number: 20150263150
    Abstract: According to one embodiment, a semiconductor device including: a first electrode; a second electrode having a portion extending toward the first electrode side; a first semiconductor layer; a first semiconductor region provided between the first semiconductor layer and the second electrode; a second semiconductor region provided between the first semiconductor region and the second electrode, and the second semiconductor region being in contact with the portion; a third electrode provided between the first electrode and the portion, and the third electrode being connected to the portion; a fourth electrode provided on the first semiconductor layer, the first semiconductor region, and the second semiconductor region via a second insulating film; and a third semiconductor region provided between the first semiconductor region and the second semiconductor region, and the third semiconductor region having a higher impurity concentration than the first semiconductor region.
    Type: Application
    Filed: September 10, 2014
    Publication date: September 17, 2015
    Inventors: Tomoko Matsudai, Tsuneo Ogura, Kazutoshi Nakamura, Ryohei Gejo
  • Patent number: 9130007
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: September 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuma Hara, Kazutoshi Nakamura, Tsuneo Ogura
  • Publication number: 20150243656
    Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.
    Type: Application
    Filed: May 11, 2015
    Publication date: August 27, 2015
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
  • Publication number: 20150236104
    Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.
    Type: Application
    Filed: May 1, 2015
    Publication date: August 20, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo OGURA, Tomoko MATSUDAI, Yuuichi OSHINO, Yoshiko IKEDA, Kazutoshi NAKAMURA, Ryohei GEJO
  • Publication number: 20150228726
    Abstract: According to one embodiment, a semiconductor device includes: first and second electrodes; a first semiconductor region being in ohmic contact with the first electrode; a second semiconductor region being in contact with the first semiconductor region and the first electrode, and the second semiconductor region having a lower impurity concentration than the first semiconductor region; a first semiconductor layer; a second semiconductor layer; a third semiconductor region; a fourth semiconductor region being in contact with the second electrode; and a third electrode in contact with the second semiconductor layer, the third semiconductor region, and the fourth semiconductor region via an insulating film.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 13, 2015
    Inventors: Tsuneo Ogura, Kazutoshi Nakamura
  • Publication number: 20150221736
    Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity-type base layer, a second conductivity-type base layer, a second semiconductor layer, a buried layer, a buried electrode, a gate insulating film, a gate electrode, and a second major electrode. The buried layer of the second conductivity type selectively is provided in the first conductivity-type base layer. The buried electrode is provided in a bottom portion of a trench which penetrates the second conductivity-type base layer to reach the buried layer. The buried electrode is in contact with the buried layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer and the buried electrode.
    Type: Application
    Filed: April 13, 2015
    Publication date: August 6, 2015
    Inventor: Tsuneo OGURA
  • Patent number: 9059236
    Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: June 16, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
  • Patent number: 9054066
    Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: June 9, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuuichi Oshino, Yoshiko Ikeda, Kazutoshi Nakamura, Ryohei Gejo
  • Patent number: 9054152
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a third semiconductor region of the first conductivity type on the second semiconductor region, a control electrode disposed within and insulated from the first, second, and third semiconductor regions, a first electrode electrically connected with the second and third semiconductor regions, a second electrode, and a fourth semiconductor region of the second conductivity type between the second electrode and the first semiconductor region. The fourth semiconductor region includes a first portion having a first dopant concentration and a second portion having a second dopant concentration higher than the first dopant concentration, and a contact area of the first portion with the second electrode is larger than a contact area of the second area with the second electrode.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Kazutoshi Nakamura