Patents by Inventor Tsuneo Ogura

Tsuneo Ogura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150155277
    Abstract: A semiconductor device includes a transistor region and diode region. A plurality of transistors is in the transistor region and at least one diode is in the diode region. The transistors include first and second body regions of a first conductivity type. The dopant concentration in the second body region is greater than the dopant concentration in the first body region. The diode includes first and second anode regions of the first conductivity type. The dopant concentration in the second anode region is greater than the dopant concentration in the first anode region. A total dopant amount in the second body region within a first block portion of the semiconductor substrate is greater than a total dopant amount in the second anode layer within a second block portion of the semiconductor substrate of the same size as the first block portion.
    Type: Application
    Filed: July 24, 2014
    Publication date: June 4, 2015
    Inventors: Tsuneo OGURA, Shinichiro MISU, Ryohei GEJO, Norio YASUHARA
  • Patent number: 9029918
    Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity-type base layer, a second conductivity-type base layer, a second semiconductor layer, a buried layer, a buried electrode, a gate insulating film, a gate electrode, and a second major electrode. The buried layer of the second conductivity type selectively is provided in the first conductivity-type base layer. The buried electrode is provided in a bottom portion of a trench which penetrates the second conductivity-type base layer to reach the buried layer. The buried electrode is in contact with the buried layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer and the buried electrode.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: May 12, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Ogura
  • Publication number: 20150091055
    Abstract: A semiconductor device includes a first region of a first conductivity type, a collector electrode electrically connected to a first side of the first region, first and second gate electrodes and first and second conductor electrodes, each of the gate and conductor electrodes extending into the first region from a second side thereof that is opposite to the first side, an emitter electrode electrically connected to the conductor electrodes, and a second region of the first conductivity type, that is adjacent to the gate electrodes, electrically connected to the emitter electrode, and spaced from the first and second conductor electrodes.
    Type: Application
    Filed: February 28, 2014
    Publication date: April 2, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryohei GEJO, Kazutoshi NAKAMURA, Tsuneo OGURA, Tomoko MATSUDAI
  • Publication number: 20150069460
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.
    Type: Application
    Filed: March 7, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takuma Hara, Kazutoshi Nakamura, Tsuneo Ogura
  • Publication number: 20150021655
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a third semiconductor region of the first conductivity type on the second semiconductor region, a control electrode disposed within and insulated from the first, second, and third semiconductor regions, a first electrode electrically connected with the second and third semiconductor regions, a second electrode, and a fourth semiconductor region of the second conductivity type between the second electrode and the first semiconductor region. The fourth semiconductor region includes a first portion having a first dopant concentration and a second portion having a second dopant concentration higher than the first dopant concentration, and a contact area of the first portion with the second electrode is larger than a contact area of the second area with the second electrode.
    Type: Application
    Filed: February 28, 2014
    Publication date: January 22, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo OGURA, Kazutoshi NAKAMURA
  • Publication number: 20150021657
    Abstract: According to one embodiment, a semiconductor device includes: first and second electrodes; a first semiconductor region being in ohmic contact with the first electrode; a second semiconductor region being in contact with the first semiconductor region and the first electrode, and the second semiconductor region having a lower impurity concentration than the first semiconductor region; a first semiconductor layer; a second semiconductor layer; a third semiconductor region; a fourth semiconductor region being in contact with the second electrode; and a third electrode in contact with the second semiconductor layer, the third semiconductor region, and the fourth semiconductor region via an insulating film.
    Type: Application
    Filed: March 10, 2014
    Publication date: January 22, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Kazutoshi Nakamura
  • Patent number: 8912632
    Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity type base layer, a second conductivity type base layer, a first conductivity type second semiconductor layer, a gate insulating film, a gate electrode, and a second major electrode. The gate insulating film is provided on a side wall of a trench penetrating the second conductivity type base layer to reach the first conductivity type base layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and electrically connected with the second semiconductor layer. A maximum impurity concentration in the second semiconductor layer is within ten times a maximum impurity concentration in the second conductivity type base layer.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Ogura
  • Patent number: 8853775
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, control electrodes disposed in trenches on the first main surface of the semiconductor substrate and extending in a first direction parallel to the first main surface, and control interconnects disposed on the first main surface of the semiconductor substrate and extending in a second direction perpendicular to the first direction. The semiconductor substrate includes a first semiconductor layer of a first conductivity type, second semiconductor layers of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, third semiconductor layers of the first conductivity type disposed on surfaces of the second semiconductor layers on the first main surface side and extending in the second direction, and a fourth semiconductor layer of the second conductivity type on the second main surface of the semiconductor substrate.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Kazutoshi Nakamura, Hideaki Ninomiya, Tomoko Matsudai, Yuichi Oshino
  • Publication number: 20140284658
    Abstract: According to one embodiment, a semiconductor device includes a first and second electrode, a first, second, third and fourth semiconductor region, and a first intermediate metal film. The first region is provided above the first electrode and has a first impurity concentration. The second region is provided above the first region and has a second impurity concentration lower than the first impurity concentration. The third region is provided above the second region and has a third impurity concentration. The fourth region is provided above the second region and has a fourth impurity concentration lower than the third impurity concentration. The second electrode is provided above the third region and the fourth region and is in ohmic contact with the third region. The intermediate metal film is provided between the second electrode and the fourth region. The intermediate metal film forms Schottky junction with the fourth region.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Matsudai, Tsuneo Ogura, Yuuichi Oshino
  • Publication number: 20140124832
    Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.
    Type: Application
    Filed: August 29, 2013
    Publication date: May 8, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
  • Publication number: 20140084333
    Abstract: In general, according to one embodiment, a power semiconductor device includes a first, a second, a third, a fourth, and a fifth electrode, and a first, a second, a third, and a fourth semiconductor layer. The first electrode includes a first and a second face. The first semiconductor layer is provided on a side of the first face of the first electrode. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The fourth semiconductor layer is provided on the third semiconductor layer. The second electrode is electrically connected to the fourth semiconductor layer. The third and fourth electrode are provided at the second semiconductor layer and the third semiconductor layer with an insulating film interposed. The fifth electrode is provided between the third electrode and the fourth electrode with an insulating film interposed.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazutoshi Nakamura, Tsuneo Ogura, Hideaki Ninomiya
  • Publication number: 20140084337
    Abstract: A collector layer of a first conductivity type is provided in the IGBT region and the boundary region and functions as a collector of the IGBT in the IGBT region. A cathode layer of a second conductivity type is provided in the diode region apart from the collector layer and functions as a cathode of the diode. A drift layer of the second conductivity type is provided in the IGBT region, the boundary region, and the diode region, the drift layer being provided on sides of the collector layer and the cathode layer opposite the first electrode. A diffusion layer of the first conductivity type is provided in the boundary region on a side of the drift layer opposite the first electrode.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Matsudai, Tsuneo Ogura, Kazutoshi Nakamura, Yuichi Oshino, Hideaki Ninomiya, Yoshiko Ikeda
  • Publication number: 20140077258
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, control electrodes disposed in trenches on the first main surface of the semiconductor substrate and extending in a first direction parallel to the first main surface, and control interconnects disposed on the first main surface of the semiconductor substrate and extending in a second direction perpendicular to the first direction. The semiconductor substrate includes a first semiconductor layer of a first conductivity type, second semiconductor layers of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, third semiconductor layers of the first conductivity type disposed on surfaces of the second semiconductor layers on the first main surface side and extending in the second direction, and a fourth semiconductor layer of the second conductivity type on the second main surface of the semiconductor substrate.
    Type: Application
    Filed: September 9, 2013
    Publication date: March 20, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Kazutoshi Nakamura, Hideaki Ninomiya, Tomoko Matsudai, Yuichi Oshino
  • Publication number: 20140070266
    Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer.
    Type: Application
    Filed: March 18, 2013
    Publication date: March 13, 2014
    Inventors: Tomoko MATSUDAI, Tsuneo OGURA, Yuichi OSHINO, Hideaki NINOMIYA, Kazutoshi NAKAMURA
  • Publication number: 20140061875
    Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo OGURA, Tomoko MATSUDAI, Yuuichi OSHINO, Yoshiko IKEDA, Kazutoshi NAKAMURA, Ryohei GEJO
  • Patent number: 8664692
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino
  • Publication number: 20130248924
    Abstract: A semiconductor device includes a reverse-conducting insulated gate bipolar transistor (IGBT), wherein the thickness of the semiconductor layer underlying the diode region of the device is thinner than the thickness of the semiconductor layer underlying the IGBT portion of the device. In one aspect, the semiconductor layer is a continuous layer, and trenches defining the anodes in the diode region extend further inwardly of the semiconductor layer than does the base regions of the IGBT portion of the device.
    Type: Application
    Filed: September 8, 2012
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko MATSUDAI, Tsuneo OGURA, Hideaki NINOMIYA
  • Publication number: 20130248882
    Abstract: In a semiconductor device, transistor cells and diode cells are formed on a single semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is formed in a transistor cell region and at a lower side of the substrate. A second semiconductor layer of the first conductivity type is formed in a region adjacent to the transistor cell region and at the lower side of the substrate. Gate electrodes are formed at an upper side of the substrate. A third semiconductor layer of the second conductivity type and a fourth semiconductor layer of the first conductivity type are formed between the gate electrodes. A fifth semiconductor layer of the first conductivity type is formed above the first semiconductor layer in the transistor cell region. A first and a second electrode are formed on both sides of the substrate.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo OGURA, Tomoko MATSUDAI, Yuichi OSHINO, Hideaki NINOMIYA
  • Publication number: 20130240947
    Abstract: A semiconductor device formed on a substrate of a first conductivity type, including a base layer of a second conductivity disposed on a first face of the substrate, an anode layer with a higher dopant amount in a portion of the base layer, an IGBT region formed on the base layer, a diode region formed on the anode layer, a trench extending from the top of the IGBT and diode regions in to the substrate. The area occupied by the diode region is different from the area occupied by the IGBT region, but they share collector and emitter electrodes. The contact area between the diode anode layer and the emitter electrode may be adjusted by the arrangement of trenches.
    Type: Application
    Filed: November 19, 2012
    Publication date: September 19, 2013
    Inventors: Tomoko Matsudai, Tsuneo Ogura
  • Publication number: 20130221401
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction.
    Type: Application
    Filed: August 30, 2012
    Publication date: August 29, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo OGURA, Tomoko MATSUDAI, Yuichi OSHINO