Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract: The present invention provides a flow detection device and numerical modeling method, the device for controlling the gas flow in the pipeline. The flow detection device includes a measurement pipe, valve control module, flow detection module and a processing module. The processing module can be detected by flow detection data a numerical model of the flow characteristics curve fitting. The processing module for feedback signal, it's for control the valve structure of open degree, with precise control of the flow.

Abstract: Embodiments of an ultraviolet (UV) curing system for treating a semiconductor substrate such as a wafer are disclosed. The curing system generally includes a processing chamber, a wafer support for holding a wafer in the chamber, a UV radiation source disposed above the chamber, and a UV transparent window interspersed between the radiation source and wafer support. In one embodiment, the wafer support is provided by a belt conveyor operable to transport wafers through the chamber during UV curing. In another embodiment, the UV radiation source is a movable lamp unit that travels across the top of the chamber for irradiating the wafer. In another embodiment, the UV transparent window includes a UV radiation modifier that reduces the intensity of UV radiation on portions of the wafer positioned below the modifier. Various embodiments enhance wafer curing uniformity by normalizing UV intensity levels on the wafer.

Abstract: The present disclosure relates to a guiding element for guiding gas flow within a chamber. The guiding element includes a structure, one or more inlets, an outlet, and a transportation region. The one or more inlets are formed on a first side of the structure. The inlets have inlet sizes selected according to a removal rate and to mitigate gas flow variations within the chamber. The outlet is on a second side of the structure, opposite the first side of the structure. The outlet has an outlet size selected according to the removal rate. The transportation region is within the structure and couples or connects the inlets to the outlet.

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) device includes a substrate including a first conductivity type, a gate positioned on the substrate, a drain region formed in the substrate, the drain region including a second conductivity type, and a source region formed in the substrate, where the source region includes at least one first part and at least one second part, the first part includes the second conductivity type, the second part includes the first conductivity type, and the first conductivity type and the second conductivity type are complementary.

Abstract: The present invention provides an intelligent air curtain fume hood, which includes cabinet, inclined air curtain module, intelligent window control module and processing module. Feature of the present invention is that the inclined air curtain module is the use of inclined air flow field distribution generated during the operation of shelter in the work space, and with variable air volume theory in order to reduce the gas leaking chance to further achieve security and energy saving effect.

Abstract: An electrostatic chuck for clamping a warped workpiece has a clamping surface comprising a dielectric layer. The dielectric layer has a field and one or more zones formed of differing dielectric materials. One or more electrodes are coupled to a power supply, and a controller controls a clamping voltage supplied to the one or more electrodes via the power supply. An electrostatic attraction force associated with each of the field and one or more zones of the dielectric layer of the electrostatic chuck is induced, wherein the electrostatic attraction force varies based on the dielectric material of each of the field and one or more zones. The electrostatic attraction force is greater in the one or more zones than in the field, therein attracting warped regions of the workpiece to the clamping surface and clamping the warped workpiece to the clamping surface across a surface of the warped workpiece.

Abstract: Embodiments that relate to mechanisms for providing a stable dislocation profile are provided. A semiconductor substrate having a gate stack is provided. An opening is formed adjacent to a side of the gate stack. A first part of an epitaxial growth structure is formed in the opening. A second part of the epitaxial growth structure is formed in the opening. The first part and the second part of the epitaxial growth structure are formed along different directions.

Abstract: A foam mat with a differently colored border includes an upper layer and a lower layer overlaid with the upper layer. The upper and lower layers are made of foaming materials of different colors, and each peripheral side of the foam mat is processed into an inclined edge where the lower layer extends further outward than the upper layer. The inclined edges show differently colored layers which are both easily identifiable and esthetically pleasing. The inclined edge at each peripheral side of the foam mat also provides a slope which reduces the chance of a user's feet hitting the foam mat by accident when the user is stepping on the foam mat.

Abstract: A device includes a pedestal. The pedestal includes a ground electrode, a central portion, and a peripheral portion. The ground electrode includes a top surface from which the peripheral portion is projected, thereby having a height difference between the central portion and the peripheral portion.

Abstract: A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region further includes a plurality of third doped regions, a plurality of gaps, and a plurality of fourth doped regions. The gaps and the third doped regions s are alternately arranged, and the fourth doped regions are formed in the gaps. The third doped regions include a second conductivity type complementary to the first conductivity type, and the fourth doped regions include the first conductivity type.

Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.

Abstract: A method of fabricating a semiconductor package is provided, including: providing a carrier having a plurality of chip areas defined thereon, and forming a connection unit on each of the chip areas; disposing a semiconductor element on each of the connection units; forming an insulating layer on the carrier and the semiconductor elements; and forming on the insulating layer a circuit layer electrically connected to the semiconductor elements. Since being formed only on the chip areas instead of on the overall carrier as in the prior art, the connection units are prevented from expanding or contracting during temperature cycle, thereby avoiding positional deviations of the semiconductor elements.

Abstract: Embodiments that relate to mechanisms for providing a stable dislocation profile are provided. A semiconductor substrate having a gate stack is provided. An opening is formed adjacent to a side of the gate stack. A first part of an epitaxial growth structure is formed in the opening. A second part of the epitaxial growth structure is formed in the opening. The first part and the second part of the epitaxial growth structure are formed along different directions.

Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.

Abstract: A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.

Abstract: A workpiece transfer system has a plurality of joints having a bearing and a primary and secondary transformer coil, wherein power provided to the primary transformer coil and secondary transformer coil of each joint produces mutual inductance between the primary and secondary transformer coil of the respective joint. A first pair of arms are rotatably coupled to a blade by a first pair of the joints, wherein the primary transformer coil of each of the first pair of joints is operably coupled to the first pair of arms, and the secondary transformer coil of each of the first pair of joints is operably coupled to the blade and an electrode beneath a dielectric workpiece retaining surface of the blade. The electrode is contactlessly energized through the transformer coils of the joint and the blade can chuck and de-chuck a workpiece by reversing current directions and by voltage adjustment.

Abstract: A layout pattern of an implant layer includes at least a linear region and at least a non-linear region. The linear region includes a plurality of first patterns to accommodate first dopants and the non-linear region includes a plurality of second patterns to accommodate the first dopants. The linear region abuts the non-linear region. Furthermore, a pattern density of the first patterns in the linear region is smaller than a pattern density of the second patterns in the non-linear region.

Abstract: An electrostatic chuck for clamping a warped workpiece has a clamping surface comprising a dielectric layer. The dielectric layer has a field and one or more zones formed of differing dielectric materials. One or more electrodes are coupled to a power supply, and a controller controls a clamping voltage supplied to the one or more electrodes via the power supply. An electrostatic attraction force associated with each of the field and one or more zones of the dielectric layer of the electrostatic chuck is induced, wherein the electrostatic attraction force varies based on the dielectric material of each of the field and one or more zones. The electrostatic attraction force is greater in the one or more zones than in the field, therein attracting warped regions of the workpiece to the clamping surface and clamping the warped workpiece to the clamping surface across a surface of the warped workpiece.

Abstract: The present disclosure provides for methods and systems for controlling profile uniformity of a chemical vapor deposition (CVD) film. A method includes depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile, and depositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile. The combined first layer and second layer have a third profile, and the first profile, the second profile, and the third profile are different from one another.