Patents by Inventor Tsung Lin

Tsung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12369250
    Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: July 22, 2025
    Assignee: Unimicron Technology Corp.
    Inventors: Ping-Tsung Lin, Kai-Ming Yang, Chia-Yu Peng, Pu-Ju Lin, Cheng-Ta Ko
  • Patent number: 12363937
    Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.
    Type: Grant
    Filed: June 26, 2024
    Date of Patent: July 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Choh Fei Yeap, Da-Wen Lin, Chih-Chieh Yeh
  • Patent number: 12356587
    Abstract: A manifold for cooling server includes an inlet pipe, an outlet pipe, a plurality of first hole groups, and a plurality of second hole groups. The distance between every two adjacent first hole groups is first distance, the distance between every two adjacent second hole groups is second distance, and the first distance is not equal to the second distance. The first distance is designed for one size of server, and the second distance is designed for another size of server. When changing the size of all servers in the rack, turning manifold 100 to 180 degrees to change the first hole groups 30 to the second hole groups 40 for adapting the severs, which makes the manifold 100 adapt two different sizes of server. A rack and a data center cooling system using the manifold are also disclosed.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: July 8, 2025
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Yu-Chia Ting, Tsung-Lin Liu
  • Patent number: 12356588
    Abstract: An immersed cooling system for cooling electronic devices includes a cooling tank accommodating coolant and multiple electronic devices and a liquid cooling circuit for circulating coolant, the electronic device includes key components and common components, the liquid cooling circuit includes cooling branches connected to the key components for cooling, the coolant in the cooling branches flows faster than the coolant in the cooling tank, which improves the heat dissipation effect of the key components and the utilization rate of the coolant by cooling the key components and the common components with different flow rates of coolant, reduces the energy consumption of the immersed cooling system and provides a more efficient thermal solution. An immersed cooling cabinet is also provided.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: July 8, 2025
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Tsung-Lin Liu, Chin-Han Chan, Yu-Chia Ting, Chun-Wei Lin, Chia-Nan Pai
  • Publication number: 20250193369
    Abstract: A virtual image display device and a stereoscopic image establishing method are provided. The virtual image display device includes a head-mounted display and an accessory. The head-mounted display performs an image capturing operation on a first region of an object to obtain first image information. The accessory has a first image capturing device for performing an image capturing operation on a second region of the object to obtain second image information. The head-mounted display establishes stereoscopic image information of the object based on the first image information and the second image information.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 12, 2025
    Applicant: HTC Corporation
    Inventors: Tsung-Lin Lu, Ching-Chia Chou, Chung-Hsiang Chang
  • Patent number: 12302611
    Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Jen Lai, Yen-Ming Chen, Tsung-Lin Lee
  • Publication number: 20250151307
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain (S/D) portion adjacent to the gate electrode, and an interlayer dielectric layer adjacent formed over the source/drain portion. The semiconductor device structure includes an etch stop layer adjacent between the source/drain portion and the interlayer dielectric layer, and a protective element adjacent formed over the interlayer dielectric layer.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Chao-Ching CHENG, Wei-Sheng YUN, Shao-Ming YU, Tsung-Lin LEE, Chih-Chieh YEH
  • Publication number: 20250136579
    Abstract: The present disclosure is directed to salts and free bases of Compounds of Formula (I), including crystalline, semi-crystalline, amorphous, and polymorph forms thereof, and processes for their preparation.
    Type: Application
    Filed: October 22, 2024
    Publication date: May 1, 2025
    Inventors: Pasit PHIASIVONGSA, Xinnan ZHANG, Chih-Tsung LIN, Asha SUNKARA
  • Publication number: 20250126750
    Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: SUNG TSANG, TSUNG-LIN LIU, YU-CHIA TING, CHENG-YI HUANG, CHIA-NAN PAI
  • Publication number: 20250120158
    Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a plurality of base regions formed over the collector region, a plurality of emitter regions formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, a plurality of base conductive layers formed over the collector region and on opposite sides of the base regions, a plurality of sidewall dielectric layers formed on top surfaces of the base conductive layers and disposed vertically between the base conductive layers and upper portions of the emitter regions, and a plurality of base contacts formed on the base conductive layers. The base contacts are divided into a first group of base contacts disposed between the base regions and a second group of base contacts disposed between the base regions and the STI region.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Jung CHEN, Chun-Ming LIN, Tsung-Lin LEE, Shiuan-Jeng LIN, Hung-Lin CHEN
  • Patent number: 12255230
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Choh-Fei Yeap, Da-Wen Lin, Chih-Chieh Yeh
  • Publication number: 20250082761
    Abstract: The invention provides dual-targeted inhibitors of bacterial RNA polymerase having the general structural formula (I): wherein a is a benzoxazino-rifamycin or a spiro-rifamycin: y is a moiety that binds to the bridge-helix N-terminus target of a bacterial RNA polymerase; and P is a bond, two bonds, or a linker. The invention also provides compositions comprising such compounds, methods of making such compounds, and methods of using said compounds. The invention has applications in control of bacterial gene expression, control of bacterial growth, antibacterial chemistry, and antibacterial therapy.
    Type: Application
    Filed: August 19, 2022
    Publication date: March 13, 2025
    Applicant: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY
    Inventors: Richard H. EBRIGHT, Yon W. EBRIGHT, Chih-Tsung LIN
  • Publication number: 20250083432
    Abstract: A method of making a mouse pad contains: bonding and hot-press molding a body and a cloth by using a first mold and a second mold. The body is made of polyurethane (PU), the second mold includes a cavity, and a size of the cavity of the second mold is equal to a predetermined size of the body, and a guide rib surrounds the cavity. The method comprising steps of: 1) flattening the body; 2) bonding the cloth on the body; 3) cutting the body in a predetermined; 4) hot-press molding the body and the cloth; 5) sublimation printing; and 6) hot-press molding to trim the mouse pad by using the first mold and of the guide rib the second mold.
    Type: Application
    Filed: July 14, 2024
    Publication date: March 13, 2025
    Inventor: Tsung-Lin Wu
  • Publication number: 20250079227
    Abstract: A wafer retaining device is provided. The wafer retaining device includes a platen configured to support a semiconductor wafer, and a retainer assembly. The retainer assembly includes a mounting member coupled to the platen, a lever, and a biasing member including a first end coupled to the lever and a second end coupled to the mounting member. The biasing member is configured to bias the lever to a closed position relative to the platen. The lever inhibits movement of the semiconductor wafer when the lever is in the closed position.
    Type: Application
    Filed: January 18, 2024
    Publication date: March 6, 2025
    Inventors: Lu-Hsun LIN, Tsung-Min LIN, Chin Tsung LIN, Hsiao-Yin HSIEH, Po-Tang TSENG
  • Patent number: 12237949
    Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.
    Type: Grant
    Filed: September 18, 2023
    Date of Patent: February 25, 2025
    Assignee: MEDIATEK INC.
    Inventors: Chung-Hsien Tsai, Che-Yu Chiang, Yu-Ting Liu, Tsung-Lin Lee, Chia-Sheng Peng, Ting-Ming Yang
  • Patent number: 12238893
    Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: February 25, 2025
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Sung Tsang, Tsung-Lin Liu, Yu-Chia Ting, Cheng-Yi Huang, Chia-Nan Pai
  • Publication number: 20250063791
    Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 20, 2025
    Inventors: Tsung-Lin Lee, Wei-Yang Lee, Ming-Chang Wen, Chien-Tai Chan, Chih Chieh Yeh, Da-Wen Lin
  • Patent number: 12230634
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Shuan Li, Tsung-Lin Lee, Chih Chieh Yeh
  • Publication number: 20250040281
    Abstract: A method of forming a device, the method including depositing a first photoresist layer over a substrate, forming an array of seed lenses by patterning and reflowing the first photoresist layer, a dimension of the array of seed lenses varying across the substrate, forming a second photoresist layer over the array of seed lenses, and forming a microlens array by patterning and reflowing the second photoresist layer.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Inventor: Yu-Tsung Lin
  • Patent number: D1063957
    Type: Grant
    Filed: October 9, 2022
    Date of Patent: February 25, 2025
    Assignee: CALYX, INC.
    Inventors: I-Ting Chen, Tsung-Lin Lu, Pei-Chi Lee, Po-Jui Chiu