Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain (S/D) portion adjacent to the gate electrode, and an interlayer dielectric layer adjacent formed over the source/drain portion. The semiconductor device structure includes an etch stop layer adjacent between the source/drain portion and the interlayer dielectric layer, and a protective element adjacent formed over the interlayer dielectric layer.

Abstract: The present disclosure is directed to salts and free bases of Compounds of Formula (I), including crystalline, semi-crystalline, amorphous, and polymorph forms thereof, and processes for their preparation.

Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.

Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a plurality of base regions formed over the collector region, a plurality of emitter regions formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, a plurality of base conductive layers formed over the collector region and on opposite sides of the base regions, a plurality of sidewall dielectric layers formed on top surfaces of the base conductive layers and disposed vertically between the base conductive layers and upper portions of the emitter regions, and a plurality of base contacts formed on the base conductive layers. The base contacts are divided into a first group of base contacts disposed between the base regions and a second group of base contacts disposed between the base regions and the STI region.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.

Abstract: A method of making a mouse pad contains: bonding and hot-press molding a body and a cloth by using a first mold and a second mold. The body is made of polyurethane (PU), the second mold includes a cavity, and a size of the cavity of the second mold is equal to a predetermined size of the body, and a guide rib surrounds the cavity. The method comprising steps of: 1) flattening the body; 2) bonding the cloth on the body; 3) cutting the body in a predetermined; 4) hot-press molding the body and the cloth; 5) sublimation printing; and 6) hot-press molding to trim the mouse pad by using the first mold and of the guide rib the second mold.

Abstract: The invention provides dual-targeted inhibitors of bacterial RNA polymerase having the general structural formula (I): wherein a is a benzoxazino-rifamycin or a spiro-rifamycin: y is a moiety that binds to the bridge-helix N-terminus target of a bacterial RNA polymerase; and P is a bond, two bonds, or a linker. The invention also provides compositions comprising such compounds, methods of making such compounds, and methods of using said compounds. The invention has applications in control of bacterial gene expression, control of bacterial growth, antibacterial chemistry, and antibacterial therapy.

Abstract: A wafer retaining device is provided. The wafer retaining device includes a platen configured to support a semiconductor wafer, and a retainer assembly. The retainer assembly includes a mounting member coupled to the platen, a lever, and a biasing member including a first end coupled to the lever and a second end coupled to the mounting member. The biasing member is configured to bias the lever to a closed position relative to the platen. The lever inhibits movement of the semiconductor wafer when the lever is in the closed position.

Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.

Abstract: A method of forming a device, the method including depositing a first photoresist layer over a substrate, forming an array of seed lenses by patterning and reflowing the first photoresist layer, a dimension of the array of seed lenses varying across the substrate, forming a second photoresist layer over the array of seed lenses, and forming a microlens array by patterning and reflowing the second photoresist layer.

Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a base region formed over the collector region, an emitter region formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, and a base dielectric layer formed over the collector region and on opposite sides of the base region. The base dielectric layer is surrounded by an inner side wall of the ring-shaped STI region.

Abstract: An information handling system includes a memory and a processor. The memory stores a current basic input/output system (BIOS) firmware image. During a regular boot mode of the information handling, the processor creates a first set of tables associated with the current BIOS firmware image, stores the first tables to the memory, and receives a BIOS firmware update image. During a BIOS update boot mode of the information handling system, the processor creates a second plurality of tables associated with the BIOS firmware update image, and compares the first and second tables. In response to a difference being determined between the first and second tables, the processor aborts the BIOS update boot mode and generate an error log.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain portion adjacent to the gate electrode, and a semiconductor layer between the gate electrode and the source/drain portion.

Abstract: An information handling system includes a memory and a processor. The memory stores a current basic input/output system (BIOS) firmware image. During a regular boot mode of the information handling, the processor creates a first set of tables associated with the current BIOS firmware image, stores the first tables to the memory, and receives a BIOS firmware update image. During a BIOS update boot mode of the information handling system, the processor creates a second plurality of tables associated with the BIOS firmware update image, and compares the first and second tables. In response to a difference being determined between the first and second tables, the processor aborts the BIOS update boot mode and generate an error log.

Abstract: A dual-valve automatic calibration system comprises a primary positioner, a first secondary positioner and a second secondary positioner: the first secondary positioner and the second secondary positioner are connected with a first fluid coating unit and a second fluid coating unit, respectively; the primary positioner comprises a primary X-axis positioner and a primary Y-axis positioner; both the first secondary positioner and the second secondary positioner are connected with the primary X-axis positioner. In contrast to the prior art that a secondary positioner is installed on a primary Z-axis positioner, a dual-valve automatic calibration system contributes to promotion of positioning precision on the Z-axis and reduction of a burden imposed on the Z-axis.

Abstract: A liquid cooling device comprises a cabinet, a liquid flowing unit, a liquid tray, and a liquid sensor. The cabinet is configured for containing an electronic component. The liquid flowing unit comprises a plurality of liquid delivery pieces connected and configured for circulating coolant to cool the electronic component. The liquid tray defines a confluence groove configured for gathering the coolant leaking from two connected ones of the plurality of liquid delivery pieces. The liquid sensor is placed in the confluence groove and is configured for sending a signal when contacting with the coolant. When the coolant leaks from two connected ones of the plurality of liquid delivery pieces then drops on the liquid tray and flows into the confluence groove by gravity, the liquid sensor contacts with the coolant in the confluence groove and sends the signal. A server with the liquid cooling device is also disclosed.