Abstract: A timing control circuit is provided to control a data voltage outputted to a pixel array of a display panel during a frame period to perform a polarity reversal every N scan lines, where N is a positive integer. The timing control circuit includes a receiver and an adjustment circuit. The receiver is configured to sequentially receive first display data and second display data for one data line of the display panel. The adjustment circuit is coupled to the receiver to adjust at least one of gray information of the second display data and charging time of the second display data according to a voltage polarity of the first display data and a voltage polarity of the second display data. A corresponding operation method of the timing control circuit is also provided.

Abstract: A method for extracting flavone aglycones in Chrysanthemum morifolium is provided. The method includes: (a) immersing a Chrysanthemum morifolium raw material in water or an aqueous solution to perform an immersion procedure for 3.5 hours or more to obtain an immersion sample; and (b) adding an extraction solvent to the immersion sample to perform an extraction procedure 5-60 minutes to obtain an extract. The Chrysanthemum morifolium raw material includes at least one of the following parts of Chrysanthemum morifolium: whole plant, roots, stems, leaves and flowers.

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

Abstract: Various strained channel transistors are disclosed herein. An exemplary semiconductor device includes a substrate and a fin structure disposed over the substrate. The fin structure includes a first epitaxial layer disposed on the substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The second epitaxial layer includes a relaxed transversal stress component and a longitudinal compressive stress component, and the third epitaxial layer has uni-axial strain. A gate structure is disposed on a channel region of the fin structure, such that the gate structure interposes a source region and a drain region of the fin structure.

Abstract: A method of forming a process film includes the following operations. A substrate is transferred into a process chamber having an interior surface. A process film is formed over the substrate, and the process film is also formed on the interior surface of the process chamber. The substrate is transferred out of the process chamber. A non-process film is formed on the interior surface of the process chamber. In some embodiments, porosity of the process film is greater than a porosity of the non-process film.

Abstract: Direct memory access data path for RAID storage is disclosed, including: receiving, at a Redundant Array of Independent Disks (RAID) controller, a request to write data to be distributed among a plurality of storage devices; computing parity information based at least in part on the data associated with the request; causing the parity information to be stored on a first subset of the plurality of storage devices; and causing the data associated with the request to be stored on a second subset of the plurality of storage devices, wherein the plurality of storage devices is configured to obtain the data associated with the request directly from a memory that is remote to the RAID controller, and wherein the data associated with the request does not pass through the RAID controller.

Abstract: A storage system and an access control method thereof are provided. The storage system receives a first I/O request from at least one hypervisor. The first I/O request is used for accessing a first disk file of disk files. The storage system then operates a first I/O operation of a first virtual disk of virtual disks according to the first I/O request since the disk files correspond to the virtual disks. The storage system reads a QoS data of the first disk file and determines a first delay period according to the QoS data. The storage system transmits a first I/O response to the at least one hypervisor after the first delay period.

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: Direct memory access data path for RAID storage is disclosed, including: receiving, at a Redundant Array of Independent Disks (RAID) controller, a request to write data to be distributed among a plurality of storage devices; computing parity information based at least in part on the data associated with the request; causing the parity information to be stored on a first subset of the plurality of storage devices; and causing the data associated with the request to be stored on a second subset of the plurality of storage devices, wherein the plurality of storage devices is configured to obtain the data associated with the request directly from a memory that is remote to the RAID controller, and wherein the data associated with the request does not pass through the RAID controller.

Abstract: A fluorescent optical system and a fluorescent image inspection system are provided. The fluorescent optical system includes a platform, at least one light source device, and at least one first filter. The platform is configured for placement of a sample to be inspected. The at least one light source device is configured to illuminate the sample to be inspected, so that the sample to be inspected is stimulated to generate a fluorescent light. The at least one first filter is correspondingly arranged in an optical path of the at least one light source device, so that an excitation light passes through the at least one first filter. An incident angle is formed between the excitation light and the platform, and the incident angle is less than 90 degrees.

Abstract: A chemical vapor deposition (CVD) apparatus is provided. The CVD apparatus includes a CVD chamber including multiple wall portions. A pedestal is disposed inside the CVD chamber, configured to support a substrate. A gas inlet port is disposed on one of the wall portions and below a substrate support portion of the pedestal. In addition, a gas flow guiding member is disposed inside the CVD chamber, coupled to the gas inlet port, and configured to dispense cleaning gases from the gas inlet port into the CVD chamber.

Abstract: A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

Abstract: A pressure sensor comprises a polysilicon sensing membrane. The pressure sensor further includes one or more polysilicon electrodes disposed over a silicon substrate. The sensor also includes one or more polysilicon routing layers that electrically connects electrodes of the one or more polysilicon electrodes to one another, wherein the polysilicon sensing membrane deforms responsive to a stimuli and changes a capacitance between the polysilicon sensing membrane and the one or more polysilicon electrodes. The sensor also includes one or more vacuum cavities positioned between the polysilicon sensing membrane and the one or more polysilicon electrodes.

Abstract: A method includes depositing a passivation layer on a substrate; depositing and patterning a first polysilicon layer on the passivation layer; depositing and patterning a first oxide layer on the first polysilicon layer forming a patterned first oxide layer; depositing and patterning a second polysilicon layer on the patterned first oxide layer. A portion of the second polysilicon layer directly contacts a portion of the first polysilicon layer. A portion of the patterned second polysilicon layer corresponds to a bottom electrode. A second oxide layer is deposited on the patterned second polysilicon layer and on an exposed portion of the patterned first oxide layer. A portion of the second oxide layer corresponding to a sensing cavity is etched, exposing the bottom electrode. Another substrate is bonded to the second oxide layer enclosing the sensing cavity. A top electrode is disposed within the another substrate and positioned over the bottom electrode.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

Abstract: A low-profile and small-size valve to a shut off a flow of fluid in a pipeline includes a frame, a tube, a moving part, a lever, an elastic part, a latch, and a trigger. The tube is movable with the moving part. The lever is rotatable around an axis. The elastic part can push the lever to rotate after the trigger pushes the buckle away from the lever to unlatch the lever and allow rotation. During the rotation of the lever, the lever pulls on the moving part, and the moving part pulls on the tube together to disconnect the tube from the pipe. The valve improves the convenience and efficiency of shutting off a flow of fluid. A pipeline and an immersion cooling system is also disclosed.

Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a base region formed over the collector region, an emitter region formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, and a base dielectric layer formed over the collector region and on opposite sides of the base region. The base dielectric layer is surrounded by an inner side wall of the ring-shaped STI region.

Abstract: The present disclosure provides a chemical supply system, including a chamber, a tubing extending into the chamber, an interlock apparatus, including a fixture for fastening the tubing, and means for determining whether the tubing is fastened by the fixture.

Abstract: A hot-swap circuit for providing soft start and overcurrent protection to an electronic circuit may include a controller and a timer. The controller may be configured to sense an electrical current associated with the hot-swap circuit, based on the electrical current sensed, perform current limiting of the electrical current to minimize inrush current to the electronic circuit, and disable the electrical current from flowing to the electronic circuit in response to the electrical current exceeding an overcurrent threshold for longer than a duration of a fault timer. The timer circuit may be configured to, for a period of time after enabling of the hot-swap circuit, cause the duration of the fault timer to be a first duration, and after the period of time, cause the duration of the fault timer to be a second duration significantly shorter than the first duration.

Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.