Abstract: A virtual image display device and a stereoscopic image establishing method are provided. The virtual image display device includes a head-mounted display and an accessory. The head-mounted display performs an image capturing operation on a first region of an object to obtain first image information. The accessory has a first image capturing device for performing an image capturing operation on a second region of the object to obtain second image information. The head-mounted display establishes stereoscopic image information of the object based on the first image information and the second image information.

Abstract: An image capturing device and an image capturing method thereof are provided. The image capturing device includes a plurality of infrared light sources, an image capturer and a controller. The infrared light sources respectively have a plurality of light types. The image capturer is configured to capture image information. The controller is coupled to the infrared light sources and the image capturer. The controller turns on or turns off each of the infrared light sources according to light intensity information, wherein at least one of the infrared light sources is turned on during an image capturing operation.

Abstract: A semiconductor device includes a fin structure over a substrate. The fin structure includes a bottom portion and a top portion. The bottom and the top portions have different materials. The device also includes a liner layer on a sidewall of the bottom portion, a dielectric layer on side surfaces of the liner layer, an interfacial layer, and a gate structure over the dielectric layer and engages the fin structure. A top surface of the liner layer extends below a bottom surface of the top portion. The interfacial layer has a first section on and directly contacting sidewall surfaces of the bottom portion and a second section on and directly contacting top and sidewall surfaces of the top portion. The gate structure includes a high-k dielectric layer and a metal gate electrode over the high-k dielectric layer. The high-k dielectric layer directly contacts the first section of the interfacial layer.

Abstract: A jetting valve with two stage calibrating structures is disclosed, the jetting valve includes: a casing having an accommodating space; a piezoelectric actuating unit disposed on one side of the accommodating space; a spraying unit disposed on the other side of the accommodating space; a displacement amplifying element is arranged at the bottom of the accommodating space and leans against on the spraying unit, the bottom end of the piezoelectric driving unit is in contact with the displacement amplifying element; a sensing unit is arranged on the periphery of the displacement amplifying element to sense the movement of the spraying unit; a control unit, connected to the sensing unit and the piezoelectric actuating unit, adjusting the voltage supplied to the piezoelectric driving unit according to data obtained by the sensing unit; and a liquid supply unit connected to the spraying unit.

Abstract: A method includes a number of operations. A plurality of isolation regions is formed between a plurality of fin structures over a substrate. A dummy gate structure is formed over the fin structures and the isolation regions. After forming the dummy gate structure, a first refilled isolation material is formed over the isolation regions. The first refilled isolation material is etched to form a plurality of first isolation layers having a top surface below top surfaces of the fin structures. A plurality of source/drain epitaxial structures is formed in the fin structures. The dummy gate structure is replaced with a gate structure.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain (S/D) portion adjacent to the gate electrode, and an interlayer dielectric layer adjacent formed over the source/drain portion. The semiconductor device structure includes an etch stop layer adjacent between the source/drain portion and the interlayer dielectric layer, and a protective element adjacent formed over the interlayer dielectric layer.

Abstract: The present disclosure is directed to salts and free bases of Compounds of Formula (I), including crystalline, semi-crystalline, amorphous, and polymorph forms thereof, and processes for their preparation.

Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.

Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a plurality of base regions formed over the collector region, a plurality of emitter regions formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, a plurality of base conductive layers formed over the collector region and on opposite sides of the base regions, a plurality of sidewall dielectric layers formed on top surfaces of the base conductive layers and disposed vertically between the base conductive layers and upper portions of the emitter regions, and a plurality of base contacts formed on the base conductive layers. The base contacts are divided into a first group of base contacts disposed between the base regions and a second group of base contacts disposed between the base regions and the STI region.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.

Abstract: The invention provides dual-targeted inhibitors of bacterial RNA polymerase having the general structural formula (I): wherein a is a benzoxazino-rifamycin or a spiro-rifamycin: y is a moiety that binds to the bridge-helix N-terminus target of a bacterial RNA polymerase; and P is a bond, two bonds, or a linker. The invention also provides compositions comprising such compounds, methods of making such compounds, and methods of using said compounds. The invention has applications in control of bacterial gene expression, control of bacterial growth, antibacterial chemistry, and antibacterial therapy.

Abstract: A method of making a mouse pad contains: bonding and hot-press molding a body and a cloth by using a first mold and a second mold. The body is made of polyurethane (PU), the second mold includes a cavity, and a size of the cavity of the second mold is equal to a predetermined size of the body, and a guide rib surrounds the cavity. The method comprising steps of: 1) flattening the body; 2) bonding the cloth on the body; 3) cutting the body in a predetermined; 4) hot-press molding the body and the cloth; 5) sublimation printing; and 6) hot-press molding to trim the mouse pad by using the first mold and of the guide rib the second mold.

Abstract: A wafer retaining device is provided. The wafer retaining device includes a platen configured to support a semiconductor wafer, and a retainer assembly. The retainer assembly includes a mounting member coupled to the platen, a lever, and a biasing member including a first end coupled to the lever and a second end coupled to the mounting member. The biasing member is configured to bias the lever to a closed position relative to the platen. The lever inhibits movement of the semiconductor wafer when the lever is in the closed position.

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.

Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.

Abstract: A method of forming a device, the method including depositing a first photoresist layer over a substrate, forming an array of seed lenses by patterning and reflowing the first photoresist layer, a dimension of the array of seed lenses varying across the substrate, forming a second photoresist layer over the array of seed lenses, and forming a microlens array by patterning and reflowing the second photoresist layer.