Abstract: A semiconductor structure includes a first epitaxial source/drain (S/D) feature disposed over a first semiconductor fin, a second epitaxial S/D feature disposed over a second semiconductor fin and adjacent to the first epitaxial S/D feature, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, a dielectric feature disposed In the ILD layer and contacting the second epitaxial S/D feature, and a conductive feature disposed in the ILD layer and contacting the first epitaxial S/D feature, where a portion of the conductive feature extends to contact the dielectric feature.

Abstract: Embodiments of the present disclosure provide semiconductor device structures. In one embodiment, the semiconductor device structure includes a gate dielectric layer, a gate electrode layer in contact with the gate dielectric layer, a first self-aligned contact (SAC) layer disposed over the gate electrode layer, an isolation layer disposed between the gate electrode layer and the first SAC layer, and a first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer.

Abstract: A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.

Abstract: A method and a system for switching multi-function modes applied in an electronic device having a plurality of hardware module functions, and includes receiving input information from a user of the electronic device; obtaining status information of the electronic device; and switching the electronic device to one of the multi-function modes according to the input information and the status information, each of the multi-function modes corresponds to at least one of the plurality of hardware module functions.

Abstract: The present invention provides a circuitry applied to multiple power domains. An amplifier of the circuitry includes an output stage and a switching circuit. The output stage includes a first transistor and a second transistor, wherein the first transistor is coupled between a supply voltage and an output terminal, the second transistor is coupled between the output terminal and a ground voltage. The switching circuit is configured to choose a body of the first transistor from the supply voltage or a reference voltage.

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

Abstract: A light source assembly includes a plurality of cells and a driving circuit. Each of the cells includes a transistor and a light source. The transistor includes a drain region that serves as a cathode of the light source. The driving circuit is configured to drive the cell. An optical sensor cell and a method for manufacturing thereof are also disclosed.

Abstract: Embodiments of the present disclosure provide semiconductor device structures. In one embodiment, the semiconductor device structure includes a gate dielectric layer, a gate electrode layer in contact with the gate dielectric layer, a first self-aligned contact (SAC) layer disposed over the gate electrode layer, an isolation layer disposed between the gate electrode layer and the first SAC layer, and a first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer.

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

Abstract: A lamp, a lamp system, a method for assembling lamp system, and a method for disassembling lamp system are described. The lamp includes a frame, a light guide plate, at least one light source and a connecting mechanism. The frame includes two side covers opposite to each other, and an accommodating space is formed between the side covers. The light guide plate is disposed in the accommodating space. The light source is disposed in at least one of the side covers and is disposed adjacent to a light incident surface of the light guide plate. The connecting mechanism is disposed in the frame. The connecting mechanism includes an engaging member and an adjusting member. The engaging member is slidably disposed in an inner space of one of the side covers.

Abstract: The present invention provides a circuitry applied to multiple power domains, wherein the circuitry includes a first circuit block and second circuit block, the first circuit block is powered by a first supply voltage of a first power domain, and the second circuit block is powered by a second supply voltage of a second power domain. The first circuit block includes a first amplifier and a switching circuit. The first amplifier is configured to receive an input signal to generate a processed input signal. When the second circuit block is powered by the second supply voltage, the switching circuit is configured to forward the processed input signal to the second circuit block; and when the second circuit block is not powered by the second supply voltage, the switching circuit disconnects a path between the first amplifier and the second circuit block.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.

Abstract: Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.

Abstract: Methods and devices that provide for a fin structure and a dielectric fin structure. A gate structure is formed over the fin structure and the hybrid fin structure. A plurality of dielectric layers is adjacent the gate structure and over the hybrid fin structure between the gate structure and a contact element over the dielectric fin structure. The plurality of dielectric layers includes an air gap, formed by removal of a dummy spacer layer.

Abstract: A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.

Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The semiconductor device structure includes a first source/drain (S/D) structure formed adjacent to the gate structure, and a first S/D contact structure formed over the first S/D structure. The semiconductor device structure includes a first filling layer formed over the first S/D structure, and the first S/D contact structure is surrounded by the first filling layer. The semiconductor device structure includes a dielectric layer formed adjacent to the gate structure and the first filling layer, and the dielectric layer and the first filling layer are made of different materials. The first filling layer is surrounded by the dielectric layer.

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes a gate stack formed across the first fin structure and a first source/drain structure formed over the first fin structure adjacent to the gate stack. The semiconductor device structure further includes a contact structure formed over the first source/drain structure and a dielectric structure formed through the contact structure. In addition, a bottom surface of the contact structure is wider than a top surface of the contact structure.