Patents by Inventor Tsung Wang

Tsung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367669
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220367194
    Abstract: In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.
    Type: Application
    Filed: September 30, 2021
    Publication date: November 17, 2022
    Inventors: Min-Hsuan LU, Kan-Ju LIN, Lin-Yu HUANG, Sheng-Tsung WANG, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI, Chih-Hao WANG
  • Publication number: 20220367379
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 17, 2022
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220359677
    Abstract: A device includes a substrate and a gate structure wrapping around at least one vertical stack of nanostructure channels. The device includes a source/drain region abutting the gate structure, and a source/drain contact over the source/drain region. The device includes an etch stop layer laterally between the source/drain contact and the gate structure and having a first sidewall in contact with the source/drain contact, and a second sidewall opposite the first sidewall. The device includes a source/drain contact isolation structure embedded in the source/drain contact and having a third sidewall substantially coplanar with the second sidewall of the etch stop layer.
    Type: Application
    Filed: September 23, 2021
    Publication date: November 10, 2022
    Inventors: Meng-Huan JAO, Lin-Yu HUANG, Sheng-Tsung WANG, Huan-Chieh SU, Cheng-Chi CHUANG, Chih-Hao WANG
  • Patent number: 11483779
    Abstract: A user equipment and a communication method are provided. The user equipment includes a signal transceiver, a first antenna, a second antenna, a third antenna, and a power amplifier module. The signal transceiver applies a conversion between a baseband signal and a radio frequency signal. The first antenna is a primary antenna for receiving and transmitting RF signals. The second antenna is a diversity antenna for receiving RF signals. The third antenna is a low frequency antenna for transmitting signals in a specific low frequency band. The power amplifier module is electrically connected to the signal transceiver, the first antenna, and the third antenna. The power amplifier module amplifies the RF signal output by the signal transceiver and outputs same to either the first or third antenna.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: October 25, 2022
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Chung-Tsung Wang, Wen-Yi Kuo
  • Patent number: 11476196
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220328637
    Abstract: A method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (CMP) process to the metal layer.
    Type: Application
    Filed: June 3, 2021
    Publication date: October 13, 2022
    Inventors: Meng-Huan Jao, Lin-Yu Huang, Sheng-Tsung Wang, Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20220270971
    Abstract: Embodiments of the present disclosure provide semiconductor device structures. In one embodiment, the semiconductor device structure includes a gate dielectric layer, a gate electrode layer in contact with the gate dielectric layer, a first self-aligned contact (SAC) layer disposed over the gate electrode layer, an isolation layer disposed between the gate electrode layer and the first SAC layer, and a first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 25, 2022
    Inventors: Sheng-Tsung WANG, Lin-Yu HUANG, Cheng-Chi Chuang, CHIH-HAO WANG
  • Publication number: 20220254927
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed within the gate capping structure and a first via structure disposed on the first contact structure.
    Type: Application
    Filed: September 9, 2021
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manfacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Sheng-Tsung Wang, Huang-Lin Chao
  • Publication number: 20220253086
    Abstract: A current mirror circuit includes a current input circuit, a current output circuit and a negative feedback circuit. A first terminal of the current input circuit receives input current, a second terminal of the current input circuit is coupled to a second terminal of the current output circuit, a first terminal of the current output circuit outputs mirror current. The negative feedback circuit includes a first transistor and a second transistor, a first terminal of the first transistor is coupled to a third terminal of the current input circuit, a second terminal of the first transistor is coupled to a second terminal of the second transistor. The first terminal of the second transistor is coupled to the third terminal of the current output circuit, the third terminal of the second transistor is grounded. The current mirror circuit improves the output impedance.
    Type: Application
    Filed: December 24, 2021
    Publication date: August 11, 2022
    Inventor: HSUAN-TSUNG WANG
  • Publication number: 20220238373
    Abstract: Semiconductor structures and methods of forming the same are provided. In one embodiment, a semiconductor structure includes an active region over a substrate, a gate structure disposed over the active region, and a gate contact that includes a lower portion disposed over the gate structure and an upper portion disposed over the lower portion.
    Type: Application
    Filed: May 5, 2021
    Publication date: July 28, 2022
    Inventors: Cheng-Chi Chuang, Huan-Chieh Su, Sheng-Tsung Wang, Lin-Yu Huang, Chih-Hao Wang
  • Publication number: 20220181206
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.
    Type: Application
    Filed: January 4, 2022
    Publication date: June 9, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Chuang, Chia-Hao Chang, Sheng-Tsung Wang, Lin-Yu Huang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220157649
    Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Inventors: Lin-Yu HUANG, Sheng-Tsung WANG, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Patent number: 11322542
    Abstract: A light-emitting diode (LED) assembly comprises a plurality of LED cells and a driving circuit. Each of the LED cells includes an LED and a transistor. The LED includes first and second LED layers and an LED electrode. The first LED layer includes a III-V compound semiconductor. The second LED layer is over the first LED layer. The LED electrode is over the second LED layer. The first LED layer is free of an LED electrode. The transistor includes a drain region connected to the first LED layer. The driving circuit is configured to drive the LED cells.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 3, 2022
    Assignee: HARVATEK CORPORATION
    Inventors: Shyi-Ming Pan, Mam-Tsung Wang, Ping-Lung Wang
  • Publication number: 20220061000
    Abstract: A user equipment and a communication method are provided. The user equipment includes a signal transceiver, a first antenna, a second antenna, a third antenna, and a power amplifier module. The signal transceiver applies a conversion between a baseband signal and a radio frequency signal. The first antenna is a primary antenna for receiving and transmitting RF signals. The second antenna is a diversity antenna for receiving RF signals. The third antenna is a low frequency antenna for transmitting signals in a specific low frequency band. The power amplifier module is electrically connected to the signal transceiver, the first antenna, and the third antenna. The power amplifier module amplifies the RF signal output by the signal transceiver and outputs same to either the first or third antenna.
    Type: Application
    Filed: July 6, 2021
    Publication date: February 24, 2022
    Inventors: CHUNG-TSUNG WANG, WEN-YI KUO
  • Patent number: 11239106
    Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20220026979
    Abstract: The present invention provides a circuitry applied to multiple power domains. An amplifier of the circuitry includes an output stage and a switching circuit. The output stage includes a first transistor and a second transistor, wherein the first transistor is coupled between a supply voltage and an output terminal, the second transistor is coupled between the output terminal and a ground voltage. The switching circuit is configured to choose a body of the first transistor from the supply voltage or a reference voltage.
    Type: Application
    Filed: May 25, 2021
    Publication date: January 27, 2022
    Inventors: Wei-Cheng Tang, Li-Lung Kao, Chia-Ling Chang, Sheng-Wei Lin, Sheng-Tsung Wang
  • Publication number: 20220028999
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Inventors: Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11217480
    Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Lin Chuang, Chia-Hao Chang, Sheng-Tsung Wang, Lin-Yu Huang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20210399693
    Abstract: The present invention provides a circuitry applied to multiple power domains, wherein the circuitry includes a first circuit block and second circuit block, the first circuit block is powered by a first supply voltage of a first power domain, and the second circuit block is powered by a second supply voltage of a second power domain. The first circuit block includes a first amplifier and a switching circuit. The first amplifier is configured to receive an input signal to generate a processed input signal. When the second circuit block is powered by the second supply voltage, the switching circuit is configured to forward the processed input signal to the second circuit block; and when the second circuit block is not powered by the second supply voltage, the switching circuit disconnects a path between the first amplifier and the second circuit block.
    Type: Application
    Filed: May 31, 2021
    Publication date: December 23, 2021
    Inventors: Wei-Cheng Tang, Li-Lung Kao, Chia-Ling Chang, Sheng-Tsung Wang, Sheng-Wei Lin