Abstract: A method for manufacturing a semiconductor device includes: forming a dielectric layer on a semiconductor structure which includes a gate structure and a pair of source/drain features disposed at opposite sides of the gate structure; patterning the dielectric layer to form an opening which exposes a corresponding one of the source/drain features; conformally forming an isolation material layer to partially fill the opening, the isolation material layer including an upper portion disposed on a top surface of the patterned dielectric layer, a lower portion disposed on the corresponding one of the source/drain features, and an interconnecting portion connecting the upper portion and the lower portion; removing the upper and lower portions; and partially removing the interconnecting portion, such that the interconnecting portion has a thickness decreasing gradually in a direction from the top surface of the patterned dielectric layer to a bottom surface of the patterned dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first depressed top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.

Abstract: A semiconductor package and the method of forming the same are provided. The semiconductor package may include a substrate, an integrated circuit package component having a semiconductor die bonded to the substrate, and a ring structure on the substrate, wherein the ring structure may encircle the integrated circuit package component in a top-down view. The ring structure may comprise a first attached segment, a second attached segment attached to the substrate by an adhesive, and a first suspended segment between the first attached segment and the second attached segment. The first suspended segment may be suspended over the substrate. The first attached segment and the second attached segment may be spaced apart from the package component by a first distance and a second distance, respectively. The first suspended segment may be spaced apart from the package component by a third distance different from the first distance and the second distance.

Abstract: The present invention provides improved processes for purifying semaglutide or liraglutide. Semaglutide or liraglutide is purified via two sequential RP-HPLC purifications followed by a salt-exchange step, where a pH is kept constant in the first and second purification steps. In particular, the processes utilize a halogenated solvent in a sample preparation step, which provides better solubility and an environment suitable for decarboxylation for crude semaglutide or liraglutide prior to a RP-HPLC purification.

Abstract: A semiconductor package module includes a package, a conductive layer, and a heat dissipating module. The package includes a semiconductor die. The conductive layer is disposed over the package. The heat dissipating module is disposed over the conductive layer, and the package and the heat dissipating module prop against two opposite sides of the conductive layer, where the heat dissipating module is thermally coupled to and electrically isolated from the package through the conductive layer.

Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A stylus and a touch device are provided. The stylus includes a tip portion and a transmission electrode. The transmission electrode is disposed on the tip portion. The transmission electrode transmits a downlink signal to the touch device. The touch device includes a touch panel and a touch processing circuit. The touch processing circuit is coupled to the touch panel. The touch processing circuit receives the downlink signal from the stylus through the touch panel. The downlink signal includes a plurality of different frequencies.

Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

Abstract: A device for detecting optical loss includes a first light-guiding cable, a second light-guiding cable, a light detector, at least one angle-adjusting bracket, and a first emission microscope. The first light-guiding cable is connected with a light generator. The light detector is connected with the second light-guiding cable. When the light generator generates a light beam, the light beam is emitted to a semiconductor light-guiding chip through the first light-guiding cable. The semiconductor light-guiding chip guides the light beam to the second light-guiding cable. The light detector receives the light beam through the second light-guiding cable to retrieve the energy of the light beam. The first emission microscope captures the leakage position of the semiconductor light-guiding chip where the light beam is emitted from the semiconductor light-guiding chip.

Abstract: A spin orbit torque magnetoresistive random access memory (SOT MRAM) includes at least a spin current source alloy layer, a ferromagnetic free layer, and an insulation layer. The spin current source alloy layer is a nickel-tungsten alloy layer. The ferromagnetic free layer is located on the spin current source alloy layer. The insulation layer is located on the ferromagnetic free layer. Since the nickel-tungsten alloy layer has favorable perpendicular magnetic anisotropic and can maintain a high spin Hall angle, it is suitable as a spin current source for the SOT MRAM.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Abstract: A wireless device includes a satellite receiver to receive data from multiple satellites. The wireless device also includes processing circuitry and memory. The memory stores one or more neural network models. The processing circuitry is operative to identify a neural network model that has been trained to adapt to a region in which the wireless device operates, classify satellite raw measurements from each satellite at a given time into a corresponding quality level using the neural network model, and identify satellite raw measurements with a quality level higher than a threshold. The location of the wireless device is calculated using the identified satellite raw measurements.

Abstract: An electric control door lock includes an inner operational device, an outer operational device, and a latch bolt operably connected to the inner and outer operational devices. A rotating shaft is rotatably supported in an activation member and includes a driving threaded in threading connection with a driving spring. When the rotating shaft is driven by a motor to rotate, the driving spring moves along a longitudinal axis to actuate the activation member. Movement of the activation member is used to control operation of the outer operational device, thereby permitting or not permitting movement of the latch bolt to the unlatching position.

Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

Abstract: In an embodiment, a method includes: forming active devices over a semiconductor substrate; forming an interconnect structure over the active devices, the interconnect structure comprising a first portion of a seal ring over the semiconductor substrate, the seal ring being electrically insulated from the active devices; forming a first passivation layer over the interconnect structure; forming a first metal pad and a second metal pad extending through the first passivation layer and over the interconnect structure, the first metal pad having a bowl shape, the second metal pad having a step shape; and depositing a second passivation layer over the first metal pad and the second metal pad.

Abstract: Semiconductor device and methods of manufacture are provided. In an embodiment, the a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface planar with the first top surface; and a first polymer buffer disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes: forming a first metal structure in a first ILD layer; planarizing the first metal structure and the first ILD layer, wherein the planarizing generates a groove at an interface of the first metal structure and the first ILD layer; forming an ESL on the first metal structure and the first ILD layer; forming a second ILD layer on the ESL; performing a first etch to remove a portion of the second ILD layer to form a first opening; performing a second etch to remove a portion of the ESL through the opening; performing a third etch to remove a portion of the first ILD layer through the first opening to form a second opening in the first ILD layer; and enlarging the second opening to connected with the groove to form a contact hole.