Abstract: An electric control door lock includes an inner operational device, an outer operational device, and a latch bolt operably connected to the inner and outer operational devices. A rotating shaft is rotatably supported in an activation member and includes a driving threaded in threading connection with a driving spring. When the rotating shaft is driven by a motor to rotate, the driving spring moves along a longitudinal axis to actuate the activation member. Movement of the activation member is used to control operation of the outer operational device, thereby permitting or not permitting movement of the latch bolt to the unlatching position.

Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

Abstract: In an embodiment, a method includes: forming active devices over a semiconductor substrate; forming an interconnect structure over the active devices, the interconnect structure comprising a first portion of a seal ring over the semiconductor substrate, the seal ring being electrically insulated from the active devices; forming a first passivation layer over the interconnect structure; forming a first metal pad and a second metal pad extending through the first passivation layer and over the interconnect structure, the first metal pad having a bowl shape, the second metal pad having a step shape; and depositing a second passivation layer over the first metal pad and the second metal pad.

Abstract: Semiconductor device and methods of manufacture are provided. In an embodiment, the a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface planar with the first top surface; and a first polymer buffer disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes: forming a first metal structure in a first ILD layer; planarizing the first metal structure and the first ILD layer, wherein the planarizing generates a groove at an interface of the first metal structure and the first ILD layer; forming an ESL on the first metal structure and the first ILD layer; forming a second ILD layer on the ESL; performing a first etch to remove a portion of the second ILD layer to form a first opening; performing a second etch to remove a portion of the ESL through the opening; performing a third etch to remove a portion of the first ILD layer through the first opening to form a second opening in the first ILD layer; and enlarging the second opening to connected with the groove to form a contact hole.

Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Abstract: A semiconductor device includes a supporting structure, a die stack, and a redistribution circuit structure. The die stack is disposed over the supporting structure and includes a first semiconductor die comprising a substrate and a second semiconductor die, where the first semiconductor die is between the second semiconductor die and the supporting structure, and a material of the supporting structure is different from a material of the substrate of the first semiconductor die. The redistribution circuit structure is disposed over the die stack and electrically coupled to the first semiconductor die and the second semiconductor die.

Abstract: A portable electronic device with a battery switching function is provided. The portable electronic device has two battery switching assemblies corresponding to each battery. Each battery switching assembly has a primary fastener and a secondary fastener corresponding to each other. When the primary fastener is engaged with the secondary fastener, the secondary fastener engages with the corresponding battery so that the battery cannot be detached from the casing of the portable electronic device. When the primary fastener and the secondary fastener are disengaged, the Hall sensor corresponding to the primary fastener sends a signal to a control unit. Then the control unit turns off the power supply of the corresponding battery and switches to another battery to supply power, or closes a specific application to reduce power consumption.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a metal line over a first substrate, a second substrate over the metal line, and a through-via penetrating through the second substrate and landing on the metal line. The through-via includes a copper fill having at least 85% (111) crystal orientation. The through-via includes a top portion with a first top width over a bottom portion with a second top width that is smaller than the first top width, and the top portion includes a first bulk portion over a first footing feature. The first bulk portion has first sidewalls, the first footing feature has second sidewalls, and the second sidewalls slant inwards from the first sidewalls to narrow the through-via from the first top width of the top portion to the second top width of the bottom portion.

Abstract: Collaborative sessions in which access to a collaborative object and added virtual content is selectively provided to participants/users. In one example of the collaborative session, a participant crops media content by use of a hand gesture to produce an image segment that can be associated to the collaborative object. The hand gesture resembles a pair of scissors and the camera and processor of the client device track a path of the hand gesture to identify an object within a displayed image to create virtual content of the identified object. The virtual content created by the hand gesture is then associated to the collaborative object.

Abstract: A particle sensing device, configured to detect a particulate concentration in a fluid, includes a detecting channel, a sensing space, a light source and a sensor. The detecting channel is configured for the fluid to flow therethrough. The sensing space is located on one side of the detecting channel and connected to the detecting channel, and the sensing space is surrounded by a surrounding wall. The light source and the sensing space are located on opposite sides of the detecting channel, and the light source is configured to emit light towards the detecting channel. The light is configured to hit at least one particle in the fluid. The sensor is disposed on an inner surface of the surrounding wall, and the sensor is configured to detect a scattered light energy generated when the light hits the particle. The sensor is a distance apart from the detecting channel.

Abstract: A semiconductor package includes a first component, a second component, and a stiffener rib. The first component is disposed on a substrate. The second component is disposed aside the first component and on the substrate. The stiffener rib is disposed between the first component and the second component. The lid is attached to the stiffener rib, the first component and the second component. The lid includes a recess portion on the stiffener rib. A first sidewall and a second sidewall of the recess portion laterally surround the stiffener rib. A first top space between a first top sidewall of the stiffener rib and the first sidewall of the recess portion is greater than a second top space between a second top sidewall of the stiffener rib and the second sidewall of the recess portion.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor fin and a second semiconductor fin over a substrate. The semiconductor device structure also includes a metal gate stack over the first semiconductor fin. The semiconductor device structure further includes a gate stack extending across edges of the first semiconductor fin and the second semiconductor fin. The gate stack has a semiconductor element and a gate dielectric layer between the semiconductor element and the substrate. The semiconductor element has a footing portion with a curved surface facing upwards, and the footing portion is a continuous part of the semiconductor element. The gate dielectric layer has a curved sidewall surface extending upward from the first semiconductor fin and ending at the curved surface of the semiconductor element.

Abstract: A semiconductor package module includes a package, a conductive layer, and a heat dissipating module. The package includes a semiconductor die. The conductive layer is disposed over the package. The heat dissipating module is disposed over the conductive layer, and the package and the heat dissipating module prop against two opposite sides of the conductive layer, where the heat dissipating module is thermally coupled to and electrically isolated from the package through the conductive layer.

Abstract: A method includes forming an n-type Fin-Field Effect Transistor (FinFET) and a p-type FinFET. The forming of the n-type FinFFT includes: forming a first auxiliary gate stack over a first semiconductor fin; forming an n-type source/drain region on the first semiconductor fin; forming a patterned interlayer dielectric (ILD) layer over the n-type source drain; depositing a first protection layer over the patterned ILD layer and the n-type source/drain region; and performing a first etch through the first protection layer. The forming of the p-type FinFET includes: forming a second auxiliary gate stack over a second semiconductor fin; forming a p-type source/drain region on the second semiconductor fin; forming the patterned ILD layer over the p-type source drain region; depositing a second protection layer over the p-type source/drain region; and performing a second etch though the second protection layer.

Abstract: A method includes forming an n-type Fin-Field Effect Transistor (FinFET) and a p-type FinFET. The forming of the n-type FinFFT includes: forming a first auxiliary gate stack over a first semiconductor fin; forming an n-type source/drain region on the first semiconductor fin adjacent to the first auxiliary gate stack; and performing a first etch to form a first recess with a first depth on a first top surface of the n-type source/drain region. The forming of the p-type FinFFT includes: forming a second auxiliary gate stack over a second semiconductor fin; forming a p-type source/drain region on the second semiconductor fin adjacent to the second auxiliary gate stack; and performing a second etch to form a second recess with a second depth on a second top surface of the p-type source/drain region. The first depth is greater than the second depth.