Patents by Inventor Tsung Yu

Tsung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250183114
    Abstract: A semiconductor package module includes a package, a conductive layer, and a heat dissipating module. The package includes a semiconductor die. The conductive layer is disposed over the package. The heat dissipating module is disposed over the conductive layer, and the package and the heat dissipating module prop against two opposite sides of the conductive layer, where the heat dissipating module is thermally coupled to and electrically isolated from the package through the conductive layer.
    Type: Application
    Filed: February 5, 2025
    Publication date: June 5, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen
  • Publication number: 20250172015
    Abstract: A lock capable of automatically locking a door after closing includes a latch, an anti-theft latch, and a stop-latch. When the door is in an open position, the stop-latch is in an extended position to prevent the anti-theft latch from moving to an anti-theft position. When the door pivots to a closed position, the stop-latch moves to a retracted position, and the anti-theft latch moves to the anti-theft position. When the latch is moved to an unlatching position through normal operation, the anti-theft latch moves to a non-anti-theft position. Thus, the anti-theft latch will be in the anti-theft position when the door is in the closed position, and the anti-theft latch will move to the non-anti-theft position when the door is opened through normal operation.
    Type: Application
    Filed: December 11, 2023
    Publication date: May 29, 2025
    Inventor: Tsung-Yu Huang
  • Publication number: 20250176088
    Abstract: An electronic device is provided. The electronic device includes a first panel including a first substrate, a second substrate, a plurality of first conductive pads, a first conductive ring, and a first electrostatic protection structure. The first substrate includes a first electronic component bonding area. The second substrate is disposed opposite to the first substrate. The plurality of first conductive pads are disposed on the first electronic component bonding area. The first conductive ring is disposed on the first substrate. The first electrostatic protection structure includes a first line end portion and a second line end portion that are opposite to each other. The first line end portion is connected to one of the plurality of first conductive pads. The second line end portion is connected to the first conductive ring. Moreover, the first conductive ring is electrically connected to a ground potential.
    Type: Application
    Filed: October 23, 2024
    Publication date: May 29, 2025
    Inventors: Tsung-Yu YANG, Ming-Huang CHEN, Chuan-Chi CHIEN
  • Patent number: 12313945
    Abstract: An electronic device including a panel is provided. The panel includes a first substrate, a second substrate opposite to the first substrate, a medium layer disposed between the first substrate and the second substrate, a sealant disposed between the first substrate and the second substrate and surrounding the medium layer, a plurality of first electrodes disposed between the first substrate and the medium layer, and a plurality of connecting lines disposed between the second substrate and the first electrodes. The sealant includes a plurality of conductive particles. The first electrodes are electrically connected to the connection lines through the conductive particles. There is a first space S1 between two adjacent connecting lines of the connecting lines. One of the conductive particles has a width of W. The first space S1 and the width W conform to the following formula: 3?S1/W?20.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: May 27, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Tsung-Yu Yang, Ming-Huang Chen, Shu-Fen Li, Chuan-Chi Chien, I-An Yao, Jui-Chu Lai
  • Patent number: 12299150
    Abstract: Collaborative sessions in which access to added virtual content is selectively made available to participants/users. A participant (the host) creates a new session and invites participants to join. The invited participants receive an invitation to join the session. The session creator (i.e., the host) and other approved participants can access the contents of a session. The session identifies a new participant when they join the session, and concurrently notifies the other participants in the session that a new participant is waiting for permission to access the added virtual content. The host or approved participants can set up the new participant with permissions for accessing added virtual content.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: May 13, 2025
    Assignee: Snap Inc.
    Inventors: Youjean Cho, Chen Ji, Fannie Liu, Andrés Monroy-Hernández, Tsung-Yu Tsai, Rajan Vaish
  • Patent number: 12297659
    Abstract: A lock case with an anti-pick function is mounted on a door. The lock case includes a latch for retaining the door in a closed position. When the door is closed, an anti-pick latch of the lock case is in a retracted position to pivot an anti-pick member of the lock case to an anti-pick position, such that the latch cannot be picked to the latching position. When the door is not closed or a connecting member of the lock case is operated to actuate the latch, the latch can move to the latching position.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: May 13, 2025
    Assignee: I-TEK METAL MFG. CO., LTD.
    Inventor: Tsung-Yu Huang
  • Publication number: 20250133760
    Abstract: A method for manufacturing a semiconductor device includes: forming a dielectric layer on a semiconductor structure which includes a gate structure and a pair of source/drain features disposed at opposite sides of the gate structure; patterning the dielectric layer to form an opening which exposes a corresponding one of the source/drain features; conformally forming an isolation material layer to partially fill the opening, the isolation material layer including an upper portion disposed on a top surface of the patterned dielectric layer, a lower portion disposed on the corresponding one of the source/drain features, and an interconnecting portion connecting the upper portion and the lower portion; removing the upper and lower portions; and partially removing the interconnecting portion, such that the interconnecting portion has a thickness decreasing gradually in a direction from the top surface of the patterned dielectric layer to a bottom surface of the patterned dielectric layer.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Pai Hsu, Chi-Ruei Yeh, Tsung-Yu Chiang
  • Patent number: 12279446
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first depressed top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.
    Type: Grant
    Filed: April 24, 2024
    Date of Patent: April 15, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yu Yang, Shin-Hung Li, Ruei-Jhe Tsao, Che-Hua Chang
  • Publication number: 20250118608
    Abstract: A semiconductor package and the method of forming the same are provided. The semiconductor package may include a substrate, an integrated circuit package component having a semiconductor die bonded to the substrate, and a ring structure on the substrate, wherein the ring structure may encircle the integrated circuit package component in a top-down view. The ring structure may comprise a first attached segment, a second attached segment attached to the substrate by an adhesive, and a first suspended segment between the first attached segment and the second attached segment. The first suspended segment may be suspended over the substrate. The first attached segment and the second attached segment may be spaced apart from the package component by a first distance and a second distance, respectively. The first suspended segment may be spaced apart from the package component by a third distance different from the first distance and the second distance.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 10, 2025
    Inventors: Wensen Hung, Yen-Fu Su, Tsung-Yu Chen
  • Patent number: 12272612
    Abstract: A semiconductor package module includes a package, a conductive layer, and a heat dissipating module. The package includes a semiconductor die. The conductive layer is disposed over the package. The heat dissipating module is disposed over the conductive layer, and the package and the heat dissipating module prop against two opposite sides of the conductive layer, where the heat dissipating module is thermally coupled to and electrically isolated from the package through the conductive layer.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen
  • Patent number: 12269844
    Abstract: The present invention provides improved processes for purifying semaglutide or liraglutide. Semaglutide or liraglutide is purified via two sequential RP-HPLC purifications followed by a salt-exchange step, where a pH is kept constant in the first and second purification steps. In particular, the processes utilize a halogenated solvent in a sample preparation step, which provides better solubility and an environment suitable for decarboxylation for crude semaglutide or liraglutide prior to a RP-HPLC purification.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: April 8, 2025
    Assignee: ScinoPharm Taiwan, Ltd.
    Inventors: Ming-Chih Wu, Tsung-Yu Hsiao
  • Patent number: 12266577
    Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung-Ling Shih, Tsung-Yu Yang, Yun-Chi Wu, Po-Wei Liu
  • Publication number: 20250105099
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Josh LIN, Chung-Jen HUANG, Yun-Chi WU, Tsung-Yu YANG
  • Patent number: 12261089
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: March 25, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsung-Yu Lin, Pei-Yu Wang, Chung-Wei Hsu
  • Patent number: 12260030
    Abstract: A stylus and a touch device are provided. The stylus includes a tip portion and a transmission electrode. The transmission electrode is disposed on the tip portion. The transmission electrode transmits a downlink signal to the touch device. The touch device includes a touch panel and a touch processing circuit. The touch processing circuit is coupled to the touch panel. The touch processing circuit receives the downlink signal from the stylus through the touch panel. The downlink signal includes a plurality of different frequencies.
    Type: Grant
    Filed: December 27, 2023
    Date of Patent: March 25, 2025
    Assignee: Novatek Microelectronics Corp.
    Inventors: Tsung-Yu Wang, Yun-Hsiang Yeh, Yuan-Fu Hsueh
  • Publication number: 20250096092
    Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
    Type: Application
    Filed: November 28, 2024
    Publication date: March 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Yu Yeh, Tsung-Shu Lin, Wei-Cheng Wu, Tsung-Yu Chen, Li-Han Hsu, Chien-Fu Tseng
  • Publication number: 20250081857
    Abstract: A spin orbit torque magnetoresistive random access memory (SOT MRAM) includes at least a spin current source alloy layer, a ferromagnetic free layer, and an insulation layer. The spin current source alloy layer is a nickel-tungsten alloy layer. The ferromagnetic free layer is located on the spin current source alloy layer. The insulation layer is located on the ferromagnetic free layer. Since the nickel-tungsten alloy layer has favorable perpendicular magnetic anisotropic and can maintain a high spin Hall angle, it is suitable as a spin current source for the SOT MRAM.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 6, 2025
    Applicant: National Tsing Hua University
    Inventors: Chih-Huang Lai, Tsung-Yu Pan, Chih-Hsiang Tseng, Yi-Cheng Tsou, Yu-Shen Yen, Rong-Zhi Chen
  • Publication number: 20250076151
    Abstract: A device for detecting optical loss includes a first light-guiding cable, a second light-guiding cable, a light detector, at least one angle-adjusting bracket, and a first emission microscope. The first light-guiding cable is connected with a light generator. The light detector is connected with the second light-guiding cable. When the light generator generates a light beam, the light beam is emitted to a semiconductor light-guiding chip through the first light-guiding cable. The semiconductor light-guiding chip guides the light beam to the second light-guiding cable. The light detector receives the light beam through the second light-guiding cable to retrieve the energy of the light beam. The first emission microscope captures the leakage position of the semiconductor light-guiding chip where the light beam is emitted from the semiconductor light-guiding chip.
    Type: Application
    Filed: January 2, 2024
    Publication date: March 6, 2025
    Inventors: CHI-LUN LIU, HSUEH-LIANG CHOU, TSUNG-YU LEE
  • Publication number: 20250069980
    Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
  • Patent number: 12228657
    Abstract: A wireless device includes a satellite receiver to receive data from multiple satellites. The wireless device also includes processing circuitry and memory. The memory stores one or more neural network models. The processing circuitry is operative to identify a neural network model that has been trained to adapt to a region in which the wireless device operates, classify satellite raw measurements from each satellite at a given time into a corresponding quality level using the neural network model, and identify satellite raw measurements with a quality level higher than a threshold. The location of the wireless device is calculated using the identified satellite raw measurements.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: February 18, 2025
    Assignee: MediaTek Inc.
    Inventors: Po-Yu Chen, Hao Chen, Tsung-Yu Chiou