Patents by Inventor Tsung Yu

Tsung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12149601
    Abstract: A method for converting network packets and a circuit system are provided. The circuit system uses firmware therein to record tables for implementing packet conversion between two types of networks (IPv4 and IPv6). In the method, a process of mapping of address and port using encapsulation (MAP-E) or a process of mapping of address and port using translation (MAP-T) is determined according to IPv4 packets routing requirement to embody an uplink and a downlink packet conversion process. A content table stores an IPv6 packet header after the MAP-E or MAP-T process. A control table is referred to for controlling the fields to be updated when adding the IPv6 packet header. A forwarding mapping rule table is referred to for determining to convert a destination IP address of an uplink IPv6 packet, or both a source IP address and a destination IP address of a downlink IPv4 packet.
    Type: Grant
    Filed: October 3, 2022
    Date of Patent: November 19, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Tsung-Yin Su, Tsung-Yu Lee
  • Patent number: 12148114
    Abstract: A collaborative session (e.g., a virtual time capsule) in which access to a collaborative object with an associated material and added virtual content is provided to users. In one example of the collaborative session, a user selects the associated material of the collaborative object. Physical characteristics are assigned to the collaborative object as a function of the associated material to be perceived by the participants when the collaborative object is manipulated. In one example, the material associated to the collaborative object is metal, wherein the interaction between the users and the collaborative object generates a response of the collaborative object that is indicative of the physical properties of metal, such as inertial, acoustic, and malleability.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: November 19, 2024
    Assignee: Snap Inc.
    Inventors: Youjean Cho, Chen Ji, Fannie Liu, Andrés Monroy-Hernández, Tsung-Yu Tsai, Rajan Vaish
  • Publication number: 20240379660
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • Publication number: 20240379771
    Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen TSENG, Po-Wei LIU, Hung-Ling SHIH, Tsung-Yu YANG, Tsung-Hua YANG, Yu-Chun CHANG
  • Publication number: 20240371794
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a cap and outer flanges. The cap overlies the semiconductor package. The outer flanges are disposed at edges of the cap, are connected with the cap, and extend towards the circuit substrate. A region of the bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Hsuan-Ning Shih, Hsien-Pin Hu, Tsung-Shu Lin, Tsung-Yu Chen, Wen-Hsin Wei
  • Publication number: 20240363611
    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Patent number: 12132111
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a semiconductor substrate and forming a dielectric layer over the semiconductor substrate to surround the first gate stack and the second gate stack. The method also includes forming a protection element to cover the second gate stack. The method further includes replacing the first gate stack with a metal gate stack after the formation of the protection element.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Wen Yang, Tsung-Yu Chiang
  • Publication number: 20240356428
    Abstract: A power converter having a multi-mode switching mechanism is provided. The power converter includes a first switch, a second switch, a low-side switch, an output calculating circuit and a control circuit. A first terminal of the first switch is connected to a first terminal of an inductor. A second terminal of the inductor is connected to an input power source. A first terminal of the second switch is connected to a second terminal of the first switch. A second terminal of the second switch is connected to the output calculating circuit. A first terminal of the low-side switch is connected to the first terminal of the first switch. A control circuit is connected to a control terminal of the first switch, a control terminal of the second switch, a control terminal of the low-side switch and the output calculating circuit.
    Type: Application
    Filed: August 7, 2023
    Publication date: October 24, 2024
    Inventors: Jen-Chien Hsieh, TSUNG-YU WU
  • Patent number: 12125757
    Abstract: A semiconductor package includes a chip package disposed on a substrate, a plurality of electronic components disposed aside the chip package on the substrate and a stiffener structure disposed on the substrate. The stiffener structure includes a stiffener ring surrounding the chip package and the plurality of electronic components, a stiffener rib between the chip package and the plurality of electronic components, wherein the stiffener rib includes a first portion and a second portion on the first portion, and a width of the second portion is greater than a width of the first portion. The semiconductor package further includes a lid attached to the stiffener structure, the chip package and the plurality of electronic components. A method of forming the semiconductor package is also provided.
    Type: Grant
    Filed: June 17, 2023
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Yu-Ling Tsai, Chien-Chia Chiu, Tsung-Yu Chen
  • Publication number: 20240347626
    Abstract: An LDMOS transistor device includes a stepped isolation structure over a substrate, a gate electrode disposed over a portion of the stepped isolation structure, a source region disposed in the substrate, and a drain region disposed in the substrate. The stepped isolation structure includes a first portion having a first thickness, and a second portion having a second thickness greater than the first thickness. The second portion includes dopants. The drain region is adjacent to the stepped isolation structure.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 17, 2024
    Inventors: TSUNG-HUA YANG, CHENG-BO SHU, CHIA-TA HSIEH, PING-CHENG LI, PO-WEI LIU, SHIH-JUNG TU, TSUNG-YU YANG, YUN-CHI WU, YU-WEN TSENG
  • Publication number: 20240339534
    Abstract: A semiconductor device includes a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate. At least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction. A thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer.
    Type: Application
    Filed: June 18, 2024
    Publication date: October 10, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Che-Hua Chang, Shin-Hung Li, Tsung-Yu Yang, Ruei-Jhe Tsao
  • Patent number: 12114503
    Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Patent number: 12104405
    Abstract: A door lock includes a latch slideably received in a case and an unlocking mechanism mounted in the case and operatively connected to the latch for moving the latch between a latching position and an unlatching position. The unlocking mechanism includes an unlocking mechanism having a shaft for moving a locking member between a front position in which the unlocking mechanism is locked and a rear position in which the unlocking mechanism is not locked. The shaft can be driven by a motor through wired or wireless control to rotate in a forward direction or reverse direction for locking or unlocking purposes.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: October 1, 2024
    Assignee: I-TEK METAL MFG. CO., LTD.
    Inventor: Tsung-Yu Huang
  • Patent number: 12103969
    Abstract: Disclosed herein is a novel monoclonal antibody exhibiting binding affinity to Siglec-3 receptor. According to the embodiment, the monoclonal antibody is capable of reversing HBV-induced immunosuppression. Accordingly, also disclosed herein are the uses thereof in the treatment and/or prophylaxis of hepatitis B virus (HBV) infection.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 1, 2024
    Assignee: Academia Sinica
    Inventors: Shie-Liang Hsieh, Tsung-Yu Tsai, An-Suei Yang, Chung-Ming Yu, Cheng-Yuan Peng
  • Publication number: 20240320353
    Abstract: A collaborative session (e.g., a virtual time capsule) in which access to a collaborative object and added virtual content is selectively provided to participants/users. In one example of the collaborative session, a participant (the host) creates a new session and invites participants to join. The session creator (i.e., the host) and other approved participants can access the contents of a session (e.g., which may be recorded using an application such as lens cloud feature; available from Snap Inc. of Santa Monica, California). A timestamp is associated with each received virtual content, and the users are provided with a timelapse of the collaborative object as a function of the timestamps.
    Type: Application
    Filed: May 31, 2024
    Publication date: September 26, 2024
    Inventors: Youjean Cho, Chen Ji, Fannie Liu, Andrés Monroy-Hernández, Tsung-Yu Tsai, Rajan Vaish
  • Patent number: 12094836
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a cap and outer flanges. The cap overlies the semiconductor package. The outer flanges are disposed at edges of the cap, are connected with the cap, and extend towards the circuit substrate. A region of the bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Hsuan-Ning Shih, Hsien-Pin Hu, Tsung-Shu Lin, Tsung-Yu Chen, Wen-Hsin Wei
  • Patent number: 12079395
    Abstract: Collaborative sessions in which access to a collaborative object and added virtual content is selectively provided to participants/users. In one example of the collaborative session, a participant crops media content by use of a hand gesture to produce an image segment that can be associated to the collaborative object. The hand gesture resembles a pair of scissors and the camera and processor of the client device track a path of the hand gesture to identify an object within a displayed image to create virtual content of the identified object. The virtual content created by the hand gesture is then associated to the collaborative object.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: September 3, 2024
    Assignee: Snap Inc.
    Inventors: Youjean Cho, Chen Ji, Fannie Liu, Andrés Monroy-Hernández, Tsung-Yu Tsai, Rajan Vaish
  • Patent number: 12080794
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: September 3, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yu Yang, Shin-Hung Li, Nien-Chung Li, Chang-Po Hsiung
  • Patent number: 12074154
    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: August 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Patent number: 12068689
    Abstract: A power converter device is provided. A feedback circuit outputs a comparison output signal. A phase-locked loop circuit provides a phase-locked signal according to a reference clock signal and an inductor voltage in a power converter circuit. An on-time circuit provides an on-time comparing signal according to the phase-locked signal, an input voltage, the inductor voltage and an output voltage of the power converter circuit. A first input terminal of an SR flip-flop receives the on-time comparing signal from the on-time circuit. A second input terminal of the SR flip-flop receives the comparison output signal from the feedback circuit. A frequency control circuit, according to changes in the input voltage and the output voltage of the power converter circuit, instantaneously adjusts the on-time of the on-time signal such that an output terminal of the SR flip-flop outputs the adjusted on-time signal to the power converter circuit.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: August 20, 2024
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Jen-Chien Hsieh, Tsung-Yu Wu