Patents by Inventor Tsung-Yu Yang

Tsung-Yu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11580637
    Abstract: The present application related to a method for detecting an object image using a convolutional neural network. Firstly, obtaining feature images by Convolution kernel, and then positioning an image of an object under detected by a default box and a boundary box from the feature image. By Comparing with the sample image, the detected object image is classifying to an esophageal cancer image or a non-esophageal cancer image. Thus, detecting an input image from the image capturing device by the convolutional neural network to judge if the input image is the esophageal cancer image for helping the doctor to interpret the detected object image.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: February 14, 2023
    Assignee: National Chung Cheng University
    Inventors: Hsiang-Chen Wang, Hao-Yi Syu, Tsung-Yu Yang, Yu-Sheng Chi
  • Patent number: 11575008
    Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yun-Chi Wu, Tsung-Yu Yang, Cheng-Bo Shu, Chien Hung Liu
  • Publication number: 20230015055
    Abstract: This application provides a method for detecting images of testing object using hyperspectral imaging. Firstly, obtaining a hyperspectral imaging information according to a reference image, hereby, obtaining corresponded hyperspectral image from an input image and obtaining corresponded feature values for operating Principal components analysis to simplify feature values. Then, obtaining feature images by Convolution kernel, and then positioning an image of an object under detected by a default box and a boundary box from the feature image. By Comparing with the esophageal cancer sample image, the image of the object under detected is classifying to an esophageal cancer image or a non-esophageal cancer image. Thus, detecting an input image from the image capturing device by the convolutional neural network to judge if the input image is the esophageal cancer image for helping the doctor to interpret the image of the object under detected.
    Type: Application
    Filed: August 5, 2021
    Publication date: January 19, 2023
    Inventors: HSIANG-CHEN WANG, TSUNG-YU YANG, YU-SHENG CHI, TING-CHUN MEN
  • Publication number: 20220406652
    Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Yu YANG, Po-Wei LIU, Yun-Chi WU, Yu-Wen TSENG, Chia-Ta HSIEH, Ping-Cheng LI, Tsung-Hua YANG, Yu-Chun CHANG
  • Patent number: 11532637
    Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Publication number: 20220384277
    Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Hung-Ling SHIH, Tsung-Yu YANG, Yun-Chi WU, Po-Wei LIU
  • Patent number: 11515404
    Abstract: A semiconductor structure includes a substrate having a first region and a second region around the first region. A first fin structure is disposed within the first region. A second fin structure is disposed within the second region. A first isolation trench is disposed within the first region and situated adjacent to the first fin structure. A first trench isolation layer is disposed in the first isolation trench. A second isolation trench is disposed around the first region and situated between the first fin structure and the second fin structure. The bottom surface of the second isolation trench has a step height. A second isolation layer is disposed in the second isolation trench.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 29, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yu Yang, Shin-Hung Li, Ruei-Jhe Tsao, Ta-Wei Chiu
  • Patent number: 11506489
    Abstract: A contour accuracy measuring system and a contour accuracy measuring method are provided. The contour accuracy measuring system captures location coordinate data of shafts of a machine tool. The location coordinate data are calculated to obtain a first true round trajectory on an inclined plane as reference information. The contour accuracy measuring system then adjusts parameters of the locations of the shafts based on the location coordinate data of the shafts of the reference information to generate a second true round trajectory on the inclined plane, so as to get to know whether the locations of the shafts after the parameters are adjusted comply with a standard. Therefore, the overall measurement process can be speeded up by automatically measuring the parameters and automatically testing an operating status.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: November 22, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Sheng Tseng, Po-Hsun Wu, Tsung-Yu Yang, Chien-Yi Lee
  • Publication number: 20220359671
    Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
    Type: Application
    Filed: September 10, 2021
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen TSENG, Po-Wei LIU, Hung-Ling SHIH, Tsung-Yu YANG, Tsung-Hua YANG, Yu-Chun CHANG
  • Publication number: 20220352142
    Abstract: Devices and methods of manufacture for a deep trench layout area-saving semiconductor structure for use with bipolar-CMOS-DMOS (BCD) devices. A semiconductor device may comprise a first BCD device formed within a first perimeter of a first BCD layout area, and a deep trench isolation structure defining the first perimeter of the first BCD layout area, in which the deep trench isolation structure may comprise a first rounded corner that may define a first corner of the first BCD layout area. A semiconductor device may comprise, a substrate, BCD device formed on the substrate, and a deep trench isolation structure laterally surrounding the BCD device. The deep trench isolation structure, with respect to a top-down view, may comprise vertical portions, horizontal portions, a “T”-shaped intersection connecting at least one vertical portion and at least one horizontal portion, and a cross-shaped intersection connecting two vertical portions and two horizontal portions.
    Type: Application
    Filed: September 21, 2021
    Publication date: November 3, 2022
    Inventors: Tsung-Yu YANG, Po-Wei LIU
  • Patent number: 11450574
    Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung-Ling Shih, Tsung-Yu Yang, Yun-Chi Wu, Po-Wei Liu
  • Patent number: 11404305
    Abstract: A manufacturing method a semiconductor device includes the following steps. A first mask pattern and a second mask pattern are formed on a first region and a second region of a substrate respectively. The second region is located adjacent to the first region. A top surface of the first mask pattern is lower than a top surface of the second mask pattern in a thickness direction of the substrate. A trench is formed in the substrate. The trench is partly located in the first region and partly located in the second region. A first etching process is performed for reducing a thickness of the second mask pattern and reducing a height difference between the top surface of the first mask pattern and the top surface of the second mask pattern in the thickness direction of the substrate. An isolation structure is formed in the trench after the first etching process.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: August 2, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ta-Wei Chiu, Shin-Hung Li, Tsung-Yu Yang, Ruei-Jhe Tsao
  • Publication number: 20220223720
    Abstract: A semiconductor structure includes a substrate having a first region and a second region around the first region. A first fin structure is disposed within the first region. A second fin structure is disposed within the second region. A first isolation trench is disposed within the first region and situated adjacent to the first fin structure. A first trench isolation layer is disposed in the first isolation trench. A second isolation trench is disposed around the first region and situated between the first fin structure and the second fin structure. The bottom surface of the second isolation trench has a step height. A second isolation layer is disposed in the second isolation trench.
    Type: Application
    Filed: January 28, 2021
    Publication date: July 14, 2022
    Inventors: Tsung-Yu Yang, Shin-Hung Li, Ruei-Jhe Tsao, Ta-Wei Chiu
  • Publication number: 20220209009
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.
    Type: Application
    Filed: January 27, 2021
    Publication date: June 30, 2022
    Inventors: Tsung-Yu Yang, Shin-Hung Li, Nien-Chung Li, Chang-Po Hsiung
  • Patent number: 11342025
    Abstract: A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen Tseng, Tsung-Yu Yang, Chung-Jen Huang
  • Patent number: 11331762
    Abstract: A method for synchronous control of a gantry mechanism with online inertia matching is applicable to a machine tool equipped with a gantry mechanism. The gantry mechanism includes two rails, a crossbeam and a saddle, in which the saddle is disposed on the crossbeam, and the crossbeam is disposed by crossing the two rails. Each of the two rails is furnished with a driving apparatus for synchronously driving the crossbeam, and the driving apparatus includes a drive motor and a lead screw. This method includes the steps of: obtaining gantry-mechanism information; detecting position information of the saddle on the crossbeam; evaluating the position information and the gantry-mechanism information to derive load-inertia variety information; and, evaluating the load-inertia variety information to adjust torque-output information of the drive motor corresponding to the respective driving apparatus.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 17, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Min-Rong Chen, Shih-Chang Liang, Tsung-Yu Yang, Jun-Hong Guo, Jih-Chieh Lee
  • Publication number: 20220084911
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Josh LIN, Chung-Jen HUANG, Yun-Chi WU, Tsung-Yu YANG
  • Publication number: 20210374949
    Abstract: The present application related to a method for detecting an object image using a convolutional neural network. Firstly, obtaining feature images by Convolution kernel, and then positioning an image of an object under detected by a default box and a boundary box from the feature image. By Comparing with the sample image, the detected object image is classifying to an esophageal cancer image or a non-esophageal cancer image. Thus, detecting an input image from the image capturing device by the convolutional neural network to judge if the input image is the esophageal cancer image for helping the doctor to interpret the detected object image.
    Type: Application
    Filed: October 27, 2020
    Publication date: December 2, 2021
    Inventors: HSIANG-CHEN WANG, HAO-YI SYU, TSUNG-YU YANG, YU-SHENG CHI
  • Patent number: 11189546
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Josh Lin, Chung-Jen Huang, Yun-Chi Wu, Tsung-Yu Yang
  • Publication number: 20210233819
    Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Inventors: Hung-Ling SHIH, Tsung-Yu YANG, Yun-Chi WU, Po-Wei LIU