Abstract: An operating method of a tracking system includes the following operations: obtaining a first relative movement vector of a client device by first movement detector; obtaining scale information related to distance; calculating a first actual movement vector of the client device according to the first relative movement vector and the scale information; and fusing, by a processor of a host device, the first relative movement vector, the scale information and the first actual movement vector to generate a 3D position of the client device.

Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Abstract: A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.

Abstract: A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.

Abstract: An object tracking method includes configuring a color of a first illuminating object to vary in a first pattern, capturing the first illuminating object according to a first color during a first time period, and capturing the first illuminating object according to a second color during a second time period after the first time period, wherein the second color is different from the first color.

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.

Abstract: A tracking system includes a trackable device and a tracking device. The trackable device has a three-dimensional shape. The trackable device includes a first orientation sensor for sensing a first orientation of the trackable device. The tracking device is communicated with the trackable device. The tracking device includes a second orientation sensor, an image sensor and a processing circuit. The second orientation sensor is configured to sense a second orientation of the tracking device. The image sensor configured to capture an image. The processing circuit is coupled with the second orientation sensor and the image sensor. The processing circuit is operable to calculate a two-dimensional silhouette corresponding to the three-dimensional shape according to the first orientation and the second orientation, and utilize the two-dimensional silhouette to search the image captured by the image sensor for allocating coordinates of the trackable device within the image.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: Disclosed is a server system having a hot plug motherboard. The server system includes a motherboard module, at least one midplane board and at least one hard disk module. The motherboard module includes a plurality of motherboards. The midplane board is coupled by means of hot plugging to each of the motherboards. The midplane board includes at least one Peripheral Component Interconnect Express (PCIe) slot, and the PCIe slot is configured to be plugged with a PCIe card. The hard disk module includes a plurality of hard disks being coupled to the PCIe card through a signal wire.

Abstract: A positioning device includes an optical sensor, an ultrasonic transceiver and a processor. The optical sensor is configured to obtain a depth image. The ultrasonic transceiver is configured to send an ultrasound and receive an ultrasound reflection. The processor is configured to target a reflective surface in the depth image, recognize a salient feature corresponding to the reflective surface in the ultrasound reflection, estimate a distance between the positioning device and reflective the surface according to a first response time of the salient feature in the ultrasound reflection.

Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.

Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.

Abstract: Disclosed is a server system having a hot plug motherboard. The server system includes a motherboard module, at least one midplane board and at least one hard disk module. The motherboard module includes a plurality of motherboards. The midplane board is coupled by means of hot plugging to each of the motherboards. The midplane board includes at least one Peripheral Component Interconnect Express (PCIe) slot, and the PCIe slot is configured to be plugged with a PCIe card. The hard disk module includes a plurality of hard disks being coupled to the PCIe card through a signal wire.