Patents by Inventor Tung

Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12322317
    Abstract: A compensating circuit and a compensating method for a pixel data of a display device are provided. The compensating circuit includes a color calculator, a gain value generator and a calculating circuit. The color calculator generates a color value according to a color of the pixel data. The gain value generator generates a first gain value according to the color value and a duty cycle of an emission driving signal, and generates a second gain value according to the duty cycle and a gray value of the pixel data. The calculating circuit calculates a compensated pixel data according to the pixel data, the first gain value and the second gain value.
    Type: Grant
    Filed: December 3, 2023
    Date of Patent: June 3, 2025
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventor: Tung-Ying Wu
  • Patent number: 12318288
    Abstract: An intravascular device delivery system has an elongated member, a guidewire receiving member, and a distal cap longitudinally fixed to a guidewire receiving member. The distal cap includes an insert having an elongate member, a rim member radially separated from the elongate member, and a wall member supporting the rim member, the wall member being disposed between the rim member and the elongate member.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 3, 2025
    Assignees: Cephea Valve Technologies, Inc., EVALVE, INC.
    Inventors: Randolf Von Oepen, Timothy C. Reynolds, Evelyn N. Haynes, Sean A McNiven, Dan Wallace, Peter Gregg, John Hill, David Tung
  • Patent number: 12319561
    Abstract: Disclosed is a coil module, comprising: a vibrating membrane suspended on an air chamber defined and supported by a first substrate, at least one planar coil, embedded in the vibrating membrane, and at least a soft magnet, embedded in the vibrating membrane and disposed surrounding at least a portion of a contour of the planar coil; wherein a substantial portion of the planar coil locates at substantially the same plane where a portion of the soft magnet is arranged.
    Type: Grant
    Filed: February 23, 2024
    Date of Patent: June 3, 2025
    Assignee: Otowahr Technology Inc.
    Inventors: Yu Min Fu, Tung Yu Wu, Tse Chih Tang
  • Patent number: 12324214
    Abstract: In some embodiments, a method for forming an integrated chip (IC) is provided. The method incudes forming an interlayer dielectric (ILD) layer over a substrate. A first opening is formed in the ILD layer and in a first region of the IC. A second opening is formed in the ILD layer and in a second region of the IC. A first high-k dielectric layer is formed lining both the first and second openings. A second dielectric layer is formed on the first high-k dielectric layer and lining the first high-k dielectric layer in both the first and second regions. The second high-k dielectric layer is removed from the first region. A conductive layer is formed over both the first and second high-k dielectric layers, where the conductive layer contacts the first high-k dielectric layer in the first region and contacts the second high-k dielectric in the second region.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Shao-Ming Yu, Tzu-Chung Wang
  • Patent number: 12324362
    Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.
    Type: Grant
    Filed: January 26, 2024
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung Ying Lee, Yu Chao Lin, Shao-Ming Yu
  • Patent number: 12324301
    Abstract: A semiconductor device comprises a substrate, a first hole-transporting layer over the substrate, a first electron-transporting layer on the first hole-transporting layer, and a second hole-transporting layer over the first electron-transporting layer. At least one of the first electron-transporting layer and the second hole-transporting layer has an organic component. The device is characterized by one of the following: a metal oxide layer present on the first electron-transporting layer, wherein a second electron-transporting layer is on the metal oxide layer, wherein the second hole-transporting layer is on the second electron-transporting layer, or the second hole transporting layer has a first p-doped hole-transporting surface present on the first electron-transporting, layer and a second p-doped hole-transporting surface facing away from the first p-doped hole-transporting surface, or the first electron-transporting layer is on a top surface and on sidewalls of the first hole-transporting layer.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: June 3, 2025
    Assignee: IMEC VZW
    Inventors: Tung Huei Ke, David Cheyns, Pawel Malinowski
  • Patent number: 12321559
    Abstract: A touch sensor panel can include a first touch electrode of a first type associated with a first touch node on the touch sensor panel, the first touch electrode electrically connected to a first trace configured to couple the first touch electrode to first touch circuitry, and a second touch electrode of a second type associated with the first touch node on the touch sensor panel, the second touch electrode electrically connected to a second trace configured to couple the second touch electrode to second touch circuitry. The first touch electrode can be formed by a solid and transparent conductive material in the touch sensor panel, the solid and transparent conductive material configured to provide shielding with respect to circuitry external to the touch sensor panel. The second touch electrode can be formed by a first metal mesh material in the touch sensor panel.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: June 3, 2025
    Assignee: Apple Inc.
    Inventors: Isaac W. Chan, Chun-Hao Tung, Sunggu Kang, John Z. Zhong
  • Patent number: 12322871
    Abstract: Antennas with integrated varactor circuits are described. The antenna may comprise metasurface antennas. In some embodiments, an antenna comprises an array of antenna elements, wherein each antenna element comprises a iris and a varactor diode integrated on an integrated circuit (IC) chip coupled across a portion of the iris. The antenna can also comprise a plurality of transistors, each transistor coupled to a distinct one of the varactor diodes in the array of antenna elements to provide a tuning voltage to the one varactor diode.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: June 3, 2025
    Assignee: KYMETA CORPORATION
    Inventors: Mohsen Sazegar, Hussein Esfahlani, Cagdas Varel, Seyed Mohamad Amin Momeni Hasan Abadi, Tung Pham, Ryan Stevenson, Witold Teller, Mohammad Ranjbarnikkhah, Paul Klassen
  • Publication number: 20250176278
    Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a semiconductor substrate, a first well region, first, second and third doped regions, and a gate structure. The first well region having a first conductivity type is located in the semiconductor substrate. The first and second doped region having a second conductivity type are located on the first well region. The third doped region having the first conductivity type is located on the first well region. The second and third doped regions are located on opposite sides of the first doped region. The gate structure is disposed on a portion of the semiconductor substrate between the first and second doped regions. A conductivity type of the gate structure is different from a conductivity type of the first and second doped regions. The gate structure is electrically connected to the first and third doped regions.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 29, 2025
    Inventors: Tzung-Lin LI, Yuan-Fu CHUNG, Tung-Hsing LEE
  • Publication number: 20250176233
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a gate structure and a first well region. The gate structure is disposed on the semiconductor substrate. The first well region having a first conductivity type is located in the semiconductor substrate. The first well region overlaps the gate structure. A first bottom of the first well region has a wave bottom surface.
    Type: Application
    Filed: November 15, 2024
    Publication date: May 29, 2025
    Inventors: Chih-Yang KAO, Yuan-Fu CHUNG, Tung-Hsing LEE
  • Publication number: 20250176442
    Abstract: A memory cell includes a bottom electrode, a top electrode, and a variable resistance layer. The top electrode is disposed over the bottom electrode. The variable resistance layer is sandwiched between the bottom electrode and the top electrode. A first portion of a bottom surface of the variable resistance layer and a second portion of the bottom surface of the variable resistance layer are parallel to each other and are located at different level heights.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 29, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chao Lin, Tung-Ying Lee, Da-Ching Chiou
  • Publication number: 20250173966
    Abstract: A system reconstructs accurate three-dimensional (3D) representation of human body from a single-view RGB-D image that includes color information and depth information. The system uses the depth information to generate a three-dimensional voxel grid and align image features with the voxels to generate voxel aligned features. The system learns geometric details of a human body from both pixel-aligned features and voxel-aligned features. The system integrates surface normal and human body semantic information to increase the accuracy of the reconstructed human body shapes. The system generates a high-fidelity 3D human shape that present high level of details that are significantly close to 3D scan captures.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 29, 2025
    Inventors: Tony Tung, Marco Pesavento
  • Publication number: 20250174497
    Abstract: A die-level parametric prediction boosting method includes acquiring a wafer map having a plurality of dies, selecting a die from the plurality of dies, inputting physical location parametric data of the die and a plurality of electrical parametric features of the die to a training model, and generating predicted data of the die by the training model according to the physical location parametric data and the plurality of electrical parametric features.
    Type: Application
    Filed: November 14, 2024
    Publication date: May 29, 2025
    Applicant: MEDIATEK INC.
    Inventors: Chin-Wei Lin, Po-Chao Tsao, Yu-Lin Yang, Cheng-Tien Wan, Tung-Hsing Lee, Chung-Kai Chang, Yi-Ju Ting, Chia-Jung Ni, Chia-Chun Sun, Cheng-Chien Huang, Yun-San Huang, Ming-Cheng Lee
  • Publication number: 20250176443
    Abstract: A memory device includes a memory cell, a protection coating, and a first sidewall spacer. The memory cell is disposed over an inter-metal dielectric (IMD) layer. The memory cell includes a bottom electrode, a top electrode and a resistance-switchable structure between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the resistance-switchable structure. The protection coating consists of a binary compound of carbon and hydrogen. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating.
    Type: Application
    Filed: January 28, 2025
    Publication date: May 29, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chao LIN, Yuan-Tien TU, Shao-Ming YU, Tung-Ying LEE
  • Publication number: 20250174498
    Abstract: A die-level parametric prediction boosting method includes acquiring mass production data of a plurality of dies, identifying a comprehensive indicator of each die according to the mass production data, generating a wafer map distribution of the plurality of dies according to a plurality of comprehensive indicators, partitioning the plurality of dies into at least two die clustering groups, and inputting a plurality of electrical parametric features of each die clustering group to a training model for generating predicted data of each die clustering group.
    Type: Application
    Filed: November 14, 2024
    Publication date: May 29, 2025
    Applicant: MEDIATEK INC.
    Inventors: Chin-Wei Lin, Chi-Ming Lee, Po-Chao Tsao, Tsung-Te Chen, Khim Jun Koh, Yu-Lin Yang, Cheng-Tien Wan, Yi-Ju Ting, Tung-Hsing Lee
  • Publication number: 20250174508
    Abstract: The present disclosure provides a semiconductor device package including a first device, a second device, and a spacer. The first device includes a substrate having a first dielectric constant. The second device includes a dielectric element, an antenna, and a reinforcing element. The dielectric element has a second dielectric constant less than the first dielectric constant. The antenna is at least partially within the dielectric element. The reinforcing element is disposed on the dielectric element, and the reinforcing element has a third dielectric constant greater than the first dielectric constant.
    Type: Application
    Filed: January 27, 2025
    Publication date: May 29, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Tung CHANG
  • Publication number: 20250174595
    Abstract: Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.
    Type: Application
    Filed: January 22, 2025
    Publication date: May 29, 2025
    Inventors: Hong-Ta Kuo, Yen-Hao Huang, I-Shi Wang, Ming-Yi Shen, Tzu-Ping Yang, Hsing-Yu Wang, Huang-Liang Lin, Yin-Tung Chou, Yuan-Hsin Chi, Sheng-Yuan Lin
  • Publication number: 20250173286
    Abstract: A cross-die interconnection monitor method includes providing a first die and a second die, embedding an intra-die detector into the first die for detecting a first feature of the first die, allocating a first inter-die detector from the first die to the second die for detecting a second feature between the first die and the second die, and comparing the first feature with the second feature for generating cross-die interconnect data from the first die to the second die by a neural network.
    Type: Application
    Filed: November 14, 2024
    Publication date: May 29, 2025
    Applicant: MEDIATEK INC.
    Inventors: Po-Chao Tsao, Tung-Hsing Lee
  • Publication number: 20250176275
    Abstract: An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes a semiconductor substrate, first and second well regions, and first and second heavily doped regions. The first and second well regions have a first conductivity type and are located in the semiconductor substrate. The first heavily doped region on the first well region has a second conductivity type. A first bottom of the first well region and a second bottom of the second well region are connected to each other and have different profiles. The first and second well regions have different doping concentrations. The second heavily doped region on the second well region has the first conductivity type. The first and second heavily doped regions are arranged side-by-side and are spaced apart from each other. The first heavily doped region is electrically connected to an input/output terminal.
    Type: Application
    Filed: November 24, 2023
    Publication date: May 29, 2025
    Inventors: Tzung-Lin LI, Yuan-Fu CHUNG, Tung-Hsing LEE
  • Publication number: 20250176240
    Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 29, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Tai CHANG, Tung-Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN