Patents by Inventor Tung

Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250210973
    Abstract: The present invention provides a DC system protection apparatus with a communication resetting function, which includes at least one load, at least one DC power supply system, a DC solid-state circuit breaker, a current sensor, a reset/break controller and a reset communication module. The at least one DC power supply system is connected to the at least one load. The DC solid-state circuit breaker is connected in series with the at least one load and the at least one DC power supply system. The current sensor is connected in series with the DC solid-state circuit breaker, the at least one load and the at least one DC power supply system. The reset/break controller is connected to the current sensor, and controls breaking and resetting of the DC solid-state circuit breaker. The reset communication module is connected to the reset/break controller.
    Type: Application
    Filed: December 24, 2023
    Publication date: June 26, 2025
    Inventors: HAN-CHUN KAO, TA-HSIU TSENG, YU-WEI LIN, CHUNG-CHING LIN, WEI-CHUN CHENG, SEN-TUNG WU, YU-KAI HUANG
  • Publication number: 20250205054
    Abstract: Prosthetic heart valve assemblies and methods, apparatus, and systems used to deliver a prosthetic heart valve assembly. A prosthetic heart valve assembly includes an inner frame, a prosthetic leaflet section disposed within the inner frame extending between in inflow row of cells and an outflow row of cells of the inner frame, and an outer support stent. The inner frame is disposed within the outer support stent, and the outer support stent is coupled and/or fastened to the inner frame. The outer support stent includes a plurality leaflet capturing arms for capturing native leaflets between the leaflet capturing arms and a portion of the prosthetic heart valve assembly when the prosthetic heart valve assembly is implanted in a native valve. For example, the native leaflets can be frictionally secured between the leaflet capturing arms of the support stent and the inner frame.
    Type: Application
    Filed: January 17, 2025
    Publication date: June 26, 2025
    Inventors: Christopher J. Olson, Glen T. Rabito, Dustin P. Armer, Minh T. Ma, Devin H. Marr, Cheng-Tung Huang, Hiroshi Okabe, Kevin M. Stewart, Alison S. Curtis, Philip P. Corso, JR.
  • Publication number: 20250205066
    Abstract: An implant being a stent is provided. The stent has a plurality of wire structures and a plurality of tube structures. The tube structures are formed on each one of the wire structures. Each one of the tube structures forms a cavity, one end of each one of the tube structures is connected to the wire structure, and another end forms an opening communicating with the cavity. Therefore, the openings formed on the implant communicate with the cavities, such that the medicine applied on the implant can flow into the cavities and not easily flow out via the openings.
    Type: Application
    Filed: March 11, 2025
    Publication date: June 26, 2025
    Inventor: TUNG-KUO TSAI
  • Publication number: 20250212132
    Abstract: An autonomous power regulation method enhances quality of the received signal under severe conditions such as weak signal, unbalanced power among antennas, and not identical power among subcarriers. The improvement in signal quality also means the better performance of the physical uplink control channel format two in the fifth generation mobile network. In terms of antenna index, symbol index, and subcarrier type, power of the received signal is autonomously compensated as the following four steps: step 1: sequence generation and reference calculation; step 2: signal extraction and magnitude calculation; step 3: threshold generation, gain calculation, and power regulation; step 4: channel estimation, channel equalization, channel decoder, and statistics. With various types of the received signal power level and wide range of signal-to-noise ratio, the provided experiment results prove that the autonomous power regulation method is effective, reliable, and versatile.
    Type: Application
    Filed: November 11, 2024
    Publication date: June 26, 2025
    Applicant: VIETTEL GROUP
    Inventors: DANG MINH PHAN, XUAN HAO LUONG, TRUNG TIEN NGUYEN, VAN HOAN DUONG, QUOC ANH HUYNH, HUU TUNG NGUYEN, MINH QUAN LAM, HUY ANH PHAM, MINH TUAN NGUYEN, QUANG HUY PHAN
  • Publication number: 20250212431
    Abstract: A semiconductor device includes an emitter, a first base encircling the emitter, a first collector encircling the emitter and the first base, a second base encircling the emitter, the first base and the first collector, and a second collector encircling the second base. The first collector is separated from the emitter by the first base, and the second collector is separated from the emitter, the first base and the first collector by the second base. The emitter, the first base, the first collector, the second base and the second collector form a concentric pattern.
    Type: Application
    Filed: December 25, 2023
    Publication date: June 26, 2025
    Inventors: TUNG-YANG LIN, HUNG-CHIH TSAI, RUEY-HSIN LIU
  • Publication number: 20250208347
    Abstract: Optical devices and methods of manufacture are presented in which interposers are incorporated with optical devices. In some embodiments a method includes embedding first optical packages within the interposers in order to provide optical bridging between different semiconductor devices. The first optical packages may be embedded with a glass core or metallization layers.
    Type: Application
    Filed: May 16, 2024
    Publication date: June 26, 2025
    Inventors: Chen-Hua Yu, Tung-Liang Shao, Yu-Sheng Huang
  • Publication number: 20250205065
    Abstract: An implant being a stent is provided and has an outer surface and multiple cavities. Multiple openings are formed on the outer surface and the cavities communicate with the openings. The maximum latitudinal section area of each cavity is larger than the area of the opening. The latitudinal section of the cavity is parallel with the outer surface of the implant. Therefore, the openings formed on the implant communicate with the cavities, such that the medicine applied on the implant can flow into the cavities. Further, because the maximum latitudinal section of each cavity is larger than the corresponding opening, after flowing into the cavities, the medicine would not easily flow out via the openings.
    Type: Application
    Filed: March 11, 2025
    Publication date: June 26, 2025
    Inventor: TUNG-KUO TSAI
  • Publication number: 20250212507
    Abstract: Contacts to n-type and p-type source/drain regions in complementary metal-oxide semiconductor (CMOS) technologies comprise a diffusion barrier layer positioned between the contact metal and the source/drain regions. The contact metal-diffusion barrier layer pairs used to contact n-type and p-type source/drain regions can comprise different materials. The contact metal layers used in n-type and p-type source/drain contacts can comprise the same or different materials. The presence of diffusion barrier layers can provide for thermally stable low resistance source/drain contacts by inhibiting dopant diffusion from the source/drain regions to the contact metal.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Nancy Zelick, Ilya V. Karpov, Christopher Jezewski, Siddharth Chouksey, Thoe Kathy Michaelos, Nazila Haratipour, Arnab Sen Gupta, I-Cheng Tung, Matthew V. Metz
  • Publication number: 20250212296
    Abstract: A device providing a notification for an urgent call, and a method therefor are provided.
    Type: Application
    Filed: March 13, 2025
    Publication date: June 26, 2025
    Inventors: Thi Phuong NGUYEN, Duy Tung NGUYEN, Van Thong DUONG, Minh Ngoc NGUYEN
  • Publication number: 20250209319
    Abstract: A deep learning compiling method for neural network model is provided. A number of predetermined execution time values required to execute a number of predetermined schedules for each operation of a neural network model in a number of different hardware backends are estimated. Based on the predetermined execution time values, one of the predetermined schedules corresponding to each operation of the hardware backends is selected as a candidate schedule corresponding to each operation of the hardware backends. The candidate schedule corresponding to each operation of the hardware backends and the corresponding candidate execution time value are recorded in a table. An intermediate representation of the neural network model is split according to the table. According to the split intermediate representations and the table, a deep learning compiling process is executed to perform the operations on at least two different hardware backends.
    Type: Application
    Filed: July 18, 2024
    Publication date: June 26, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kuen-Wey Lin, Shun-Ho Lee, Yan-Ying Li, Ming-Chih Tung
  • Patent number: 12342548
    Abstract: An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Cheng-Hsien Wu, Cheng-Chun Chang, Elia Ambrosi, Hengyuan Lee, Ying-Yu Chen, Xinyu Bao, Tung-Ying Lee
  • Patent number: 12342561
    Abstract: A high-electron mobility transistor includes a substrate, a buffer layer over the substrate, a barrier layer over the buffer layer, and a gate structure on the barrier layer. The gate structure includes a cap layer and a gate over the cap layer. The cap layer includes a gate-leakage suppressing region on its sidewall.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: June 24, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Wen-Jung Liao
  • Patent number: 12341026
    Abstract: A chemical dispensing system is capable of simultaneously supplying a semiconductor processing chemical for production and testing through the use of independent chemical supply lines, which reduces production downtime of an associated semiconductor process, increases throughput and capability of the semiconductor process, and/or the like. Moreover, the capability to simultaneously supply the semiconductor processing chemical for production and testing allows for an increased quantity of semiconductor processing chemical batches to be tested with minimal impact to production, which increases quality control over the semiconductor processing chemical. In addition, the independent chemical supply lines may be used to supply the semiconductor processing chemical to production while independently filtering semiconductor processing chemical directly from a storage drum through a filtration loop.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chieh Hsu, Yung-Long Chen, Fang-Pin Chiang, Feng-An Yang, Ching-Jung Hsu, Chi-Tung Lai
  • Patent number: 12342579
    Abstract: A semiconductor device includes a substrate, a first transistor disposed on the substrate, a second transistor in proximity to the first transistor on the substrate, at least one interlayer dielectric layer covering the first transistor and the second transistor, a first stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the first transistor, and a second stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the second transistor.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: June 24, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Yu Yang, Fang-Yun Liu, Chien-Tung Yue, Kuo-Liang Yeh, Mu-Kai Tsai, Jinn-Horng Lai, Cheng-Hsiung Chen
  • Patent number: 12341081
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Grant
    Filed: January 4, 2024
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Patent number: 12342489
    Abstract: An adjustable bracket for enclosing an open frame power supply unit (PSU) is disclosed. The adjustable bracket includes a first bracket section having a first primary plate and a first secondary plate extending generally vertically from one end of the first primary plate; and a second bracket section having a second primary plate and a second secondary plate extending generally vertically from one end of the second primary plate, the first secondary plate and the second secondary plate being generally parallel such that the first secondary plate faces the second secondary plate. The second primary plate is movably coupled to the first primary plate such that the adjustable bracket can be in a compact, intermediately extended, or fully extended configuration by adjusting the bracket according to a width of the open frame PSU, the width being different for a first open frame PSU than for a second open frame PSU.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: June 24, 2025
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yaw-Tzorng Tsorng, Ming-Lung Wang, Hung-Wei Chen, Tung-Shiun Yang
  • Patent number: 12339916
    Abstract: Systems and methods for dynamic user profile management are provided. One aspect of the systems and methods includes receiving, by a lookup component, a request for a user profile; computing, by a profile component, a time-to-live (TTL) refresh value for the user profile based on a lookup history of the user profile; updating, by the profile component, a TTL value of the user profile based on the request and the TTL refresh value; storing, by the profile component, the user profile and the updated TTL value in the edge database; and removing, by the edge database, the user profile from the edge database based on the updated TTL value.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: June 24, 2025
    Assignee: ADOBE INC.
    Inventors: Nathan Ng, Tung Mai, Thomas Greger, Kelly Quinn Nicholes, Antonio Cuevas, Saayan Mitra, Somdeb Sarkhel, Anup Bandigadi Rao, Ryan A. Rossi, Viswanathan Swaminathan, Shivakumar Vaithyanathan
  • Patent number: 12342536
    Abstract: A semiconductor memory device including an array region and a peripheral region surrounding the array region. The array region includes a plurality of active regions and a first insulating layer disposed between the active regions. The peripheral region includes a peripheral structure, a second insulating layer surrounding the peripheral structure, and a third insulating layer surrounding the second insulating layer. At least a buried word line extends through the array region and the peripheral region, wherein a portion of the buried word line through the second insulating layer comprises a neck profile from a plan view.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: June 24, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Yu-Cheng Tung
  • Publication number: 20250203146
    Abstract: A High-Definition Multimedia Interface (HDMI) signal detection method is provided. The HDMI signal detection method may be applied to an apparatus (e.g., a sink device). The HDMI signal detection method may include the following steps. The apparatus may receive input data from a source apparatus through an HDMI standard, wherein the input data comprises a plurality of data sets. Then, the apparatus may compare each data set to a predefined reference pattern according to a slide window with the predefined reference pattern to generate a comparison result. Then, the apparatus may determine whether the total match count corresponding to the comparison result is less than a threshold to determine the HDMI standard corresponding to the input data.
    Type: Application
    Filed: November 8, 2024
    Publication date: June 19, 2025
    Inventors: Chen-Yi LIU, Ko-Yin LAI, Chih-Wei CHOU, Kuo-Chang CHENG, You-Tsai JENG, Chin-Lung LIN, Hung-Yu SU, Chi-Chih CHEN, Tai-Lai TUNG
  • Patent number: D1080931
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: June 24, 2025
    Assignee: LIGITEK ELECTRONICS CO., LTD.
    Inventors: Yi-Wen Chen, Wen-Chung Chou, I-Hsin Tung