Patents by Inventor Tzu-Hung Lin

Tzu-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for householder of mansion to manage entrance by smart phone
    Patent number: 10089805
    Abstract: The present invention provides a method for householder of mansion to manage entrance by smart phone, so that the householder can manage entrance at outside. When a visitor pushes a doorbell of a mansion door machine, the householder at outside uses a smart phone to conduct audio and video communication with the visitor. If the householder agrees to let the visitor go in, the householder instructs the smart phone to generate a password for the visitor to memorize and let the visitor enter the mansion. The password is also sent to a home door machine of the householder. When the visitor an ives the home door machine of the householder, input the password. If the password inputted by the visitor is the same as the password generated by the smart phone, then the home door will open to let the visitor go in.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 2, 2018
    Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Shaw Hwa Hwang, Bing Chih Yao, Kuan Lin Chen, Yao Hsing Chung, Chi Jung Huang, Cheng Yu Yeh, Shun Chieh Chang, Li Te Shen, Ning Yun Ku, Tzu Hung Lin, Ming Che Yeh
  • Semiconductor structure
    Patent number: 10090375
    Abstract: The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 2, 2018
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Cheng-Chou Hung
  • SEMICONDUCTOR PACKAGE STRUCTURE
    Publication number: 20180269164
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a wiring structure. The semiconductor package structure also includes a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The semiconductor package structure further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The first semiconductor die and the second semiconductor die are separated by a molding material. In addition, the semiconductor package structure includes a first hole and a second hole formed on the second surface of the substrate.
    Type: Application
    Filed: February 27, 2018
    Publication date: September 20, 2018
    Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG, Nai-Wei LIU
  • Semiconductor chip package assembly with improved heat dissipation performance
    Patent number: 10079192
    Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 18, 2018
    Assignee: MediaTek Inc.
    Inventors: Ching-Wen Hsiao, Tzu-Hung Lin, I-Hsuan Peng, Tung-Hsien Hsieh, Sheng-Ming Chang
  • SEMICONDUCTOR PACKAGE ASSEMBLY
    Publication number: 20180233452
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package overlying a portion of the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure, a first semiconductor die and a molding compound. The first semiconductor die is disposed on a first surface of the first RDL structure and electrically coupled to the first RDL structure. The molding compound is positioned overlying the first semiconductor die and the first surface of the first RDL structure. The second semiconductor package includes a first memory die and a second memory die vertically stacked on the first memory die. The second memory die is electrically coupled to first memory die by through silicon via (TSV) interconnects formed passing through the second memory die.
    Type: Application
    Filed: February 8, 2018
    Publication date: August 16, 2018
    Inventors: Tzu-Hung LIN, Chia-Cheng CHANG, I-Hsuan PENG
  • Semiconductor package assembly with facing active surfaces of first and second semiconductor die and method for forming the same
    Patent number: 10032756
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 24, 2018
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Semiconductor package assembly
    Patent number: 9997498
    Abstract: In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 12, 2018
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Semiconductor package assembly
    Patent number: 9978729
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on a bottom surface of the first molding compound. The first semiconductor die is coupled to the first RDL structure. A second redistribution layer (RDL) structure is disposed on a top surface of the first molding compound. A passive device is coupled to the second RDL structure.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: May 22, 2018
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng
  • Semiconductor package assembly with through silicon via interconnect
    Patent number: 9947624
    Abstract: The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. The assembly further includes a second semiconductor die mounted on the first semiconductor package, having a ground pad thereon. One of the TSV interconnects of the first semiconductor package has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 17, 2018
    Assignee: MediaTek Inc.
    Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin, Kuei-Ti Chan, Ruey-Beei Wu, Kai-Bin Wu
  • SEMICONDUCTOR PACKAGE WITH IMPROVED BANDWIDTH
    Publication number: 20180102343
    Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.
    Type: Application
    Filed: July 10, 2017
    Publication date: April 12, 2018
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Nai-Wei Liu, Wei-Che Huang
  • Fan-out package structure having embedded package substrate
    Patent number: 9941260
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: April 10, 2018
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Chi-Chin Lien, Nai-Wei Liu, I-Hsuan Peng, Ching-Wen Hsiao, Wei-Che Huang
  • Semiconductor package structure and method for forming the same
    Patent number: 9899261
    Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 20, 2018
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Chou Hung, Ming-Tzong Yang, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin
  • SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20170373038
    Abstract: A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first electronic component, a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component, a molding compound on the first electronic component and surrounding the second electronic component, a third electronic component stacked on the second electronic component and the molding compound.
    Type: Application
    Filed: September 6, 2017
    Publication date: December 28, 2017
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG
  • SEMICONDUCTOR PACKAGE ASSEMBLY
    Publication number: 20170338175
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.
    Type: Application
    Filed: April 7, 2017
    Publication date: November 23, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Che-Hung KUO, Che-Ya CHOU, Wei-Che HUANG
  • MONITOR FOR DYNAMIC DISPLAYING
    Publication number: 20170316663
    Abstract: The present invention provides a monitor for dynamic displaying. K cameras are connected with the monitor in order to display images recorded by the k cameras on a screen of the monitor. An “abnormality detection algorithm” is used for detecting abnormalities of the images recorded by the k cameras. Those images having abnormalities are displayed continuously on the screen, other images having no abnormality are not displayed, so that a security service personnel can watch those images having abnormalities on the screen to enable appropriate action quickly.
    Type: Application
    Filed: May 2, 2016
    Publication date: November 2, 2017
    Inventors: Shaw Hwa HWANG, Bing Chih YAO, Kuan Lin CHEN, Yao Hsing CHUNG, Chi Jung HUANG, Cheng Yu YEH, Shun Chieh CHANG, Li Te SHEN, Chao Ping CHU, Ning Yun KU, Tzu Hung LIN, Ming Che YEH
  • METHOD OF PREVENTING PRY FOR RANDOM ACCESS MEMORY
    Publication number: 20170316218
    Abstract: The present invention provides a method of preventing pry for random access memory. A functional interface is designed between a computer program and a random access memory. When the computer program wants to store an original data into the random access memory, an encryption procedure is processed on the original data first, and then stoic into the random access memory for being an encrypted data. When the computer program ants to fetch related data float the random access memory, the functional interface is used to fetch the encrypted data for decryption, so that the original data is obtained for calculation.
    Type: Application
    Filed: May 2, 2016
    Publication date: November 2, 2017
    Inventors: Shaw Hwa HWANG, Bing Chih YAO, Kuan Lin CHEN, Yao Hsing CHUNG, Chi Jung HUANG, Cheng Yu YEH, Shun Chieh CHANG, Li Te SHEN, Chao Ping CHU, Ning Yun KU, Tzu Hung LIN, Ming Che YEH
  • Semiconductor package structure having first and second guard ring regions of different conductivity types and method for forming the same
    Patent number: 9786560
    Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 10, 2017
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Chou Hung, Ming-Tzong Yang, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang, Tzu-Hung Lin
  • Semiconductor package structure and method for forming the same
    Patent number: 9786632
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor package structure also includes a second electronic component stacked on the first electronic component. The active surface of the first electronic component faces the active surface of the second electronic component. The semiconductor package structure further includes a molding compound on the first electronic component and surrounding the second electronic component. In addition, the semiconductor package structure includes a third electronic component stacked on the second electronic component and the molding compound.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: October 10, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • SEMICONDUCTOR PACKAGE ASSEMBLY
    Publication number: 20170287877
    Abstract: In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG
  • Registration method for managing NAT shutdown
    Patent number: 9781171
    Abstract: The present invention provides a registration method for managing NAT shutdown. In Internet communication field, a user must perform registrations intermittently to a server through NAT, and increase the time interval of registration step by step. But NAT itself will shutdown if no packet is passed through for a long period. The registration method of the present invention is to adjust the time interval of registration step by step so that the time interval of registration is slightly less than the shutdown time of NAT, and then fix the time interval of registration to assure that all of the Invite packet can pass through without blocking up by the shutdown of NAT.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 3, 2017
    Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Shaw Hwa Hwang, Cheng Yu Yeh, Kuan Lin Chen, Yao Hsing Chung, Chi Jung Huang, Li Te Shen, Shun Chieh Chang, Bing Chih Yao, Chao Ping Chu, Ning Yun Ku, Tzu Hung Lin, Ming Che Yeh