Abstract: A semiconductor device includes transistor cells with vertical channels perpendicular to a first surface of a semiconductor portion. A buried compensation structure in the semiconductor portion between the transistor cells and a second surface of the semiconductor portion parallel to the first surface includes first areas and second areas. The first and second areas are alternatingly arranged along a lateral direction parallel to the first surface. A contiguous impurity layer of a first conductivity type separates the transistor cells from the buried compensation structure.

Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Abstract: A semiconductor arrangement includes a semiconductor body and a power transistor including a source region, a drain region, a body region and a drift region arranged in the semiconductor body, a gate electrode arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric. The semiconductor arrangement further includes a high voltage device arranged within a well-like dielectric structure in the semiconductor body and comprising a further drift region.

Abstract: A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal. The half-bridge circuit further includes a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.

Abstract: A super junction semiconductor device includes a semiconductor portion with a first surface and a second surface parallel to the first surface. The semiconductor portion includes a doped layer of a first conductivity type formed at least in a cell area. The super junction semiconductor device further includes columnar first super junction regions of a second, opposite conductivity type extending in a direction perpendicular to the first surface and separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A distance between the first super junction regions and the second surface does not exceed 30 ?m.

Abstract: A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement.

Abstract: In a semiconductor substrate with a first surface and a working surface parallel to the first surface, columnar first and second super junction regions of a first and a second conductivity type are formed. The first and second super junction regions extend in a direction perpendicular to the first surface and form a super junction structure. The semiconductor portion is thinned such that, after the thinning, a distance between the first super junction regions having the second conductivity type and a second surface obtained from the working surface does not exceed 30 ?m. Impurities are implanted into the second surface to form one or more implanted zones. The embodiments combine super junction approaches with backside implants enabled by thin wafer technology.

Abstract: The present disclosure provides a semiconductor device, including a compensation area that includes p-regions and n-regions, a plurality of transistor cells including gate electrodes on the compensation area, and one or more interconnections for electrically connecting gate electrodes. The gate electrodes may have a width smaller than ½ of a pitch of the cells.

Abstract: The present disclosure provides a semiconductor device and an integrated apparatus having the same. The semiconductor device includes a substrate, a buffer layer on the substrate, a compensation area which includes a p-region and a n-region on the buffer layer, and a transistor cell on the compensation area. The transistor cell includes a source region, a body region, a gate electrode and a gate dielectric formed at least between the gate electrode and the body region. The gate dielectric has a thickness in a range of 12 nm to 50 nm.

Abstract: According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns.

Abstract: A super junction semiconductor device includes a semiconductor portion with a first surface and a parallel second surface. A doped layer of a first conductivity type is formed at least in a cell area. Columnar first super junction regions of a second, opposite conductivity type extend in a direction perpendicular to the first surface. Columnar second super junction regions of the first conductivity type separate the first super junction regions from each other. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A distance between the first super junction regions and the second surface does not exceed 30 ?m. The on-state or forward resistance of low-voltage devices rated for reverse breakdown voltages below 1000 V can be defined by the resistance of the super junction structure.

Abstract: A signal transmission arrangement is disclosed. A voltage converter includes a signal transmission arrangement.

Abstract: According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns.

Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Abstract: A semiconductor device includes transistor cells with vertical channels perpendicular to a first surface of a semiconductor portion. A buried compensation structure in the semiconductor portion between the transistor cells and a second surface of the semiconductor portion parallel to the first surface includes first areas and second areas. The first and second areas are alternatingly arranged along a lateral direction parallel to the first surface. A contiguous impurity layer of a first conductivity type separates the transistor cells from the buried compensation structure.

Abstract: According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns.

Abstract: A lateral trench transistor has a semiconductor body having a source region, a source contact, a body region, a drain region, and a gate trench, in which a gate electrode which is isolated from the semiconductor body is embedded. A heavily doped semiconductor region is provided within the body region or adjacent to it, and is electrically connected to the source contact, and whose dopant type corresponds to that of the body region.

Abstract: A drift layer of a super junction semiconductor device includes first portions of a first conductivity type and second portions of a second conductivity type opposite to the first conductivity type. The first and second portions are formed both in a cell area and in an edge area surrounding the cell area, wherein an on-state or forward current through the drift layer flows through the first portions in the cell area. At least one of the first and second portions other than the first portions in the cell area includes an auxiliary structure or contains auxiliary impurities to locally reduce the avalanche rate. Locally reducing the avalanche rate increases the total voltage blocking capability of the super junction semiconductor device.

Abstract: A method for production of doped semiconductor regions in a semiconductor body of a lateral trench transistor includes forming a trench in the semiconductor body and introducing dopants into at least one area of the semiconductor body that is adjacent to the trench, by carrying out a process in which dopants enter the at least one area through inner walls of the trench.

Abstract: According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns.