Patents by Inventor Van H. Le
Van H. Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128269Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Inventors: Abhishek A. SHARMA, Van H. LE, Seung Hoon SUNG, Ravi PILLARISETTY, Marko RADOSAVLJEVIC
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Patent number: 11950407Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.Type: GrantFiled: March 24, 2020Date of Patent: April 2, 2024Assignee: Intel CorporationInventors: Juan G. Alzate Vinasco, Travis W. Lajoie, Abhishek A. Sharma, Kimberly L Pierce, Elliot N. Tan, Yu-Jin Chen, Van H. Le, Pei-Hua Wang, Bernhard Sell
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Publication number: 20240105852Abstract: Top-gate thin film transistor (TFTs) structures. Thin film transistors when in the top-gate configuration suffer from contact resistance. An example TFT includes a semiconductor layer doped with one or more dopant elements. A gate dielectric layer is on the semiconductor layer, and a gate electrode is on the gate dielectric layer. The semiconductor layer is doped with the one or more dopant elements beneath the gate dielectric layer. The TFT may further include one or more contacts and/or one or more gate spacers, and the semiconductor layer may further be doped with the one or more dopant elements beneath the contact(s) and/or gate spacer(s).Type: ApplicationFiled: December 8, 2023Publication date: March 28, 2024Applicant: Intel CorporationInventors: Abhishek A. Sharma, Sean T. Ma, Van H. Le, Jack T. Kavalieros, Gilbert Dewey
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Patent number: 11923371Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.Type: GrantFiled: September 29, 2017Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Seung Hoon Sung, Ravi Pillarisetty, Marko Radosavljevic
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Publication number: 20240055531Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.Type: ApplicationFiled: October 25, 2023Publication date: February 15, 2024Applicant: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung, Yih Wang, Tahir Ghani
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Publication number: 20240049450Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Jared STOEGER, Yu-Wen HUANG, Shu ZHOU
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Patent number: 11894465Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.Type: GrantFiled: February 12, 2021Date of Patent: February 6, 2024Assignee: Google LLCInventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
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Patent number: 11895824Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.Type: GrantFiled: February 8, 2022Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Ravi Pillarisetty, Van H. Le, Gilbert Dewey, Abhishek A Sharma
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Patent number: 11881517Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.Type: GrantFiled: April 19, 2022Date of Patent: January 23, 2024Inventors: Abhishek Sharma, Cory Weber, Van H. Le, Sean Ma
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Patent number: 11862728Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.Type: GrantFiled: October 1, 2021Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung, Yih Wang, Tahir Ghani
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Patent number: 11862729Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).Type: GrantFiled: January 25, 2022Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Yih Wang, Abhishek Sharma, Sean Ma, Van H. Le
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Patent number: 11862730Abstract: Described is a thin film transistor which comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer.Type: GrantFiled: May 27, 2022Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Abhishek A. Sharma, Sean T. Ma, Van H. Le, Jack T. Kavalieros, Gilbert Dewey
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Patent number: 11843054Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.Type: GrantFiled: June 22, 2018Date of Patent: December 12, 2023Assignee: Intel CorporationInventors: Van H. Le, Seung Hoon Sung, Benjamin Chu-Kung, Miriam Reshotko, Matthew Metz, Yih Wang, Gilbert Dewey, Jack Kavalieros, Tahir Ghani, Nazila Haratipour, Abhishek Sharma, Shriram Shivaraman
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Patent number: 11837648Abstract: Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.Type: GrantFiled: March 15, 2022Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Seung Hoon Sung, Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani
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Publication number: 20230387315Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.Type: ApplicationFiled: July 27, 2023Publication date: November 30, 2023Inventors: Abhishek A. SHARMA, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Gilbert DEWEY
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Patent number: 11832438Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.Type: GrantFiled: June 28, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Jared Stoeger, Yu-Wen Huang, Shu Zhou
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Publication number: 20230369501Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: Intel CorporationInventors: Cheng Tan, Yu-Wen Huang, Hui-Min Chuang, Xiaojun Weng, Nikhil J. Mehta, Allen B. Gardiner, Shu Zhou, Timothy Jen, Abhishek Anil Sharma, Van H. Le, Travis W. Lajoie, Bernhard Sell
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Publication number: 20230369444Abstract: Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: Intel CorporationInventors: Abhishek Anil Sharma, Albert B. Chen, Mark Armstrong, Afrin Sultana, Van H. Le, Travis W. Lajoie, Shailesh Kumar Madisetti, Timothy Jen, Cheng Tan, Moshe Dolejsi, Vishak Venkatraman, Christopher Ryder, Deepyanti Taneja
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Publication number: 20230369509Abstract: Techniques are provided herein for forming thin film transistor (TFT) structures having one or more doped contact regions. The addition of certain dopants can be used to increase conductivity and provide higher thermal stability in the contact regions of the TFT. Memory structures having TFT structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the TFT structures within the memory structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: Intel CorporationInventors: Jisoo Kim, Xiaoye Qin, Timothy Jen, Harish Ganapathy, Van H. Le, Huiying Liu, Prem Chanani, Cheng Tan, Shailesh Kumar Madisetti, Abhishek Anil Sharma, Brian Wadsworth, Vishak Venkatraman, Andre Baran
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Publication number: 20230371233Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: Intel CorporationInventors: Abhishek Anil Sharma, Travis W. Lajoie, Forough Mahmoudabadi, Shailesh Kumar Madisetti, Van H. Le, Timothy Jen, Cheng Tan, Jisoo Kim, Miriam R. Reshotko, Vishak Venkatraman, Eva Vo, Yue Zhong, Yu-Che Chiu, Moshe Dolejsi, Lorenzo Ferrari, Akash Kannegulla, Deepyanti Taneja, Mark Armstrong, Kamal H. Baloch, Afrin Sultana, Albert B. Chen, Vamsi Evani, Yang Yang, Juan G. Alzate-Vinasco, Fatih Hamzaoglu