Patents by Inventor Van H. Le

Van H. Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12191395
    Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.
    Type: Grant
    Filed: October 25, 2023
    Date of Patent: January 7, 2025
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung, Yih Wang, Tahir Ghani
  • Patent number: 12183831
    Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 31, 2024
    Assignee: Intel Corporation
    Inventors: Van H. Le, Abhishek A. Sharma, Benjamin Chu-Kung, Gilbert Dewey, Ravi Pillarisetty, Miriam R. Reshotko, Shriram Shivaraman, Li Huey Tan, Tristan A. Tronic, Jack T. Kavalieros
  • Patent number: 12148734
    Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Elliot Tan, Hui Jae Yoo, Noriyuki Sato, Travis W. Lajoie, Van H. Le, Thoe Michaelos
  • Patent number: 12150297
    Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Noriyuki Sato, Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Arnab Sen Gupta, Matthew V. Metz, Elliot N. Tan, Hui Jae Yoo, Travis W. Lajoie, Van H. Le, Pei-Hua Wang
  • Patent number: 12142689
    Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: November 12, 2024
    Assignee: Intel Corporation
    Inventors: Sean Ma, Abhishek Sharma, Gilbert Dewey, Jack T. Kavalieros, Van H. Le
  • Patent number: 12125917
    Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: October 22, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey
  • Patent number: 12119409
    Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
  • Publication number: 20240339410
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component, including an organic dielectric material; a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes metal contacts and a dielectric material between adjacent ones of the metal contacts, and wherein the dielectric material includes an inorganic dielectric material; and a third microelectronic component coupled to the first microelectronic component by wire bonding or solder.
    Type: Application
    Filed: June 18, 2024
    Publication date: October 10, 2024
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Feras Eid, Randy B. Osborne, Van H. Le
  • Patent number: 12080781
    Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Noriyuki Sato, Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Elliot N. Tan, Hui Jae Yoo, Travis W. Lajoie, Van H. Le, Pei-Hua Wang, Jason Peck, Tobias Brown-Heft
  • Patent number: 12058847
    Abstract: Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: August 6, 2024
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Abhishek A. Sharma, Charles Kuo, Brian S. Doyle, Urusa Shahriar Alaan, Van H Le, Elijah V. Karpov, Kaan Oguz, Arnab Sen Gupta
  • Patent number: 12057402
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include an interposer, including an organic dielectric material, and a microelectronic component coupled to the interposer by direct bonding.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 6, 2024
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Feras Eid, Randy B. Osborne, Van H. Le
  • Patent number: 12009433
    Abstract: Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: June 11, 2024
    Assignee: Intel Corporation
    Inventors: Van H. Le, Inanc Meric, Gilbert Dewey, Sean Ma, Abhishek A. Sharma, Miriam Reshotko, Shriram Shivaraman, Kent Millard, Matthew V. Metz, Wilhelm Melitz, Benjamin Chu-Kung, Jack Kavalieros
  • Patent number: 11997847
    Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Shriram Shivaraman, Yih Wang, Tahir Ghani, Jack T. Kavalieros
  • Patent number: 11991873
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Yu-Wen Huang, Shu Zhou
  • Patent number: 11978804
    Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Yih Wang
  • Publication number: 20240128269
    Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Inventors: Abhishek A. SHARMA, Van H. LE, Seung Hoon SUNG, Ravi PILLARISETTY, Marko RADOSAVLJEVIC
  • Patent number: 11950407
    Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Juan G. Alzate Vinasco, Travis W. Lajoie, Abhishek A. Sharma, Kimberly L Pierce, Elliot N. Tan, Yu-Jin Chen, Van H. Le, Pei-Hua Wang, Bernhard Sell
  • Publication number: 20240105852
    Abstract: Top-gate thin film transistor (TFTs) structures. Thin film transistors when in the top-gate configuration suffer from contact resistance. An example TFT includes a semiconductor layer doped with one or more dopant elements. A gate dielectric layer is on the semiconductor layer, and a gate electrode is on the gate dielectric layer. The semiconductor layer is doped with the one or more dopant elements beneath the gate dielectric layer. The TFT may further include one or more contacts and/or one or more gate spacers, and the semiconductor layer may further be doped with the one or more dopant elements beneath the contact(s) and/or gate spacer(s).
    Type: Application
    Filed: December 8, 2023
    Publication date: March 28, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Sean T. Ma, Van H. Le, Jack T. Kavalieros, Gilbert Dewey
  • Patent number: 11923371
    Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Seung Hoon Sung, Ravi Pillarisetty, Marko Radosavljevic
  • Patent number: RE50222
    Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: November 26, 2024
    Assignee: Sony Group Corporation
    Inventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Jack T. Kavaileros, Robert S. Chau, Jessica S. Kachian