Patents by Inventor Van H. Le

Van H. Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190305138
    Abstract: Described is a thin film transistor which comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Sean T. Ma, Van H. Le, Jack T. Kavalieros, Gilbert Dewey
  • Publication number: 20190305136
    Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Sean MA, Abhishek SHARMA, Gilbert DEWEY, Jack T. KAVALIEROS, Van H. LE
  • Publication number: 20190305137
    Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung, Yih Wang, Tahir Ghani
  • Publication number: 20190304982
    Abstract: A method is described. The method includes forming bit line structures above bitline contact structures, forming a first material on top surfaces and sidewall surfaces of the bit line structures to establish step structures for via formation, and forming a second material on the top surface of the first material. Capacitor landing structures are formed by patterning the second material.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Abhishek A. SHARMA, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Yih WANG, Benjamin CHU-KUNG, Shriram SHIVARAMAN
  • Publication number: 20190305121
    Abstract: Techniques and mechanisms for providing efficient transistor functionality of an integrated circuit. In an embodiment, a transistor device comprises a first body of a high mobility semiconductor and a second body of a wide bandgap semiconductor. The first body adjoins each of, and is disposed between, the second body and a gate dielectric layer of the transistor. The second body extends between, and variously adjoins, each of a source of the transistor and a drain of the transistor. A location of the second body mitigates current leakage that might otherwise occur via the first body. In another embodiment, a mobility of the first body is equal to or greater than 100 cm2/V·s, wherein a bandgap of the second body is equal to or greater than 2.0 eV.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Gilbert Dewey, Van H. Le, Willy Rachmady, Ravi Pillarisetty
  • Publication number: 20190305101
    Abstract: Techniques and mechanisms for improved performance characteristics of a transistor device. In an embodiment, a transistor of an integrated circuit comprises a source, a drain, a gate, a gate dielectric and a semiconductor structure which adjoins the gate dielectric. The semiconductor structure is configured to provide a conductive channel between the source and drain. The semiconductor structure includes first, second and third portions, the second portion between the source and the gate, and the third portion between the drain and the gate, wherein the first portion connects the second portion and third portion to one another. A thickness of the first portion is less than another thickness of one of the second portion or the third portion. In another embodiment, the locations of thicker portions of semiconductor structure mitigate overall transistor capacitance, while a thinner intermediary portion of the semiconductor structure promotes good sub-threshold swing characteristics.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Sean T. Ma, Jack Kavalieros, Benjamin Chu-Kung
  • Publication number: 20190304974
    Abstract: Techniques and mechanisms for providing a space efficient complementary metal-oxide-semiconductor (CMOS) circuit. In an embodiment, a p-type transistor of a circuit is to conduct current in a direction parallel to a surface of a semiconductor substrate, wherein an n-type thin film transistor (TFT) of the circuit is to conduct current in a direction which is orthogonal to the surface. A first interconnect is directly coupled to each of the two transistors, wherein the first interconnect, a high mobility channel structure of the n-type TFT, and a source or drain of the p-type transistor are on the same line of direction. A second interconnect comprises a conductive path which extends to respective gates of the p-type transistor and the n-type TFT, wherein the conductive path is limited to a region over a footprint of the p-type transistor. In another embodiment, functionality of a logical inverter is provided with the circuit.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Willy Rachmady, Ravi Pillarisetty
  • Publication number: 20190296104
    Abstract: A thin film transistor (TFT) apparatus is disclosed, where the apparatus includes a gate comprising metal, a source and a drain, a semiconductor body, and two or more dielectric structures between the gate and the semiconductor body. In an example, the two or more dielectric structures may include at least a first dielectric structure having a first bandgap and a second dielectric structure having a second bandgap. The first bandgap may be different from the second bandgap. The TFT apparatus may be a back-gated TFT apparatus where the source is at least in part coplanar with the drain, and the gate is non-coplanar with the source and the drain.
    Type: Application
    Filed: March 20, 2018
    Publication date: September 26, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Willy Rachmady, Van H. Le, Gilbert Dewey, Ravi Pillarisetty
  • Patent number: 10418487
    Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Jessica S. Kachian
  • Publication number: 20190273133
    Abstract: Disclosed herein are transistor amorphous interlayer arrangements, and related methods and devices. For example, in some embodiments, transistor amorphous interlayer arrangement may include a channel material and a transistor source/drain stack. The transistor source/drain stack may include a transistor electrode material configured to be a transistor source/drain contact, i.e. either a source contact or a drain contact of the transistor, and a doped amorphous semiconductor material disposed between the transistor electrode material and the channel material.
    Type: Application
    Filed: December 14, 2016
    Publication date: September 5, 2019
    Applicant: Intel Corporation
    Inventors: Ashish Agrawal, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey, Glenn A. Glass, Van H. Le, Anand S. Murthy, Jack T. Kavalieros, Matthew V. Metz, Willy Rachmady
  • Patent number: 10403733
    Abstract: Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Ashish Agrawal, Benjamin Chu-Kung, Van H. Le, Matthew V. Metz, Willy Rachmady, Jack T. Kavalieros, Rafael Rios
  • Publication number: 20190259844
    Abstract: Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 22, 2019
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Tahir Ghani, Jack T. Kavalieros, Gilbert Dewey, Van H. Le, Lawrence D. Wong, Christopher J. Jezewski
  • Publication number: 20190259850
    Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.
    Type: Application
    Filed: June 9, 2016
    Publication date: August 22, 2019
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Van H. Le, Jeanette M. Roberts, David J. Michalak, James S. Clarke, Zachary R. Yoscovits
  • Patent number: 10388733
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros
  • Patent number: 10388800
    Abstract: A thin film transistor (TFT) device is provided, where the TFT may include a plurality of stacked structures comprising metal oxide. In an example, any two adjacent structures of the plurality of stacked structures may be separated by a corresponding intervening structure. In an example, the TFT may also include gate dielectric material on at least a first side and a second side of the plurality of stacked structures. In an example, the TFT may further include a gate electrode comprising a first section and a second section, where the first and second sections of the gate electrode may be respectively on the first side and the second side of the plurality of stacked structures.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack Kavalieros, Tahir Ghani
  • Publication number: 20190252020
    Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.
    Type: Application
    Filed: September 30, 2016
    Publication date: August 15, 2019
    Inventors: Rafael RIOS, Abhishek Anil SHARMA, Van H. LE, Gilbert William DEWEY, Jack T. KAVALIEROS
  • Publication number: 20190214466
    Abstract: An embodiment includes a device comprising: a substrate; a dielectric layer on the substrate and including a trench; a first portion of the trench including a first material that comprises at least one of a group III-V material and a group IV material; and a second portion of the trench, located between the first portion and the substrate, which includes a second material and an upper region and a lower region; wherein: (a)(i) the second material in the upper region has fewer defects than the second material in the lower region, and (a)(ii) the first material is strained. Other embodiments are described herein.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 11, 2019
    Inventors: Benjamin Chu-Kung, Van H. Le, Ashish Agrawal, Jack T. Kavalieros, Matthew V. Metz, Seung Hoon Sung, Rafael Rios, Gilbert Dewey
  • Patent number: 10347767
    Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Van H. Le, Ravi Pillarisetty, Gilbert Dewey, Jack T. Kavalieros, Ashish Agrawal
  • Patent number: 10340275
    Abstract: A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Jack T. Kavalieros, Robert S. Chau, Niloy Mukherjee, Rafael Rios, Prashant Majhi, Van H. Le, Ravi Pillarisetty, Uday Shah, Gilbert Dewey, Marko Radosavljevic
  • Publication number: 20190198675
    Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.
    Type: Application
    Filed: September 27, 2016
    Publication date: June 27, 2019
    Inventors: ABHISHEK A. SHARMA, VAN H. LE, GILBERT DEWEY, RAFAEL RIOS, JACK T. KAVALIEROS, YIH WANG, SHRIRAM SHIVARAMAN