Patents by Inventor Van H. Le

Van H. Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031503
    Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
  • Patent number: 11031499
    Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Van H. Le, Matthew V. Metz, Benjamin Chu-Kung, Ashish Agrawal, Jack T. Kavalieros
  • Publication number: 20210167216
    Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Publication number: 20210139388
    Abstract: There is provided a smart release potash fertilizer granule comprising a potash core; an extended release layer covering the potash core, wherein the extended release layer comprises water-swellable copolymeric nanoparticles and at least one water-soluble organic acid or water-soluble organic carboxylate salt; a controlled release layer covering the extended release layer, wherein the controlled release layer comprises water-swellable copolymeric nanoparticles; and an anticaking layer covering the controlled release layer, wherein the anticaking layer comprises water-insoluble copolymeric nanoparticles.
    Type: Application
    Filed: February 6, 2019
    Publication date: May 13, 2021
    Inventors: My T. NGUYEN, Hoa V. TRAN, Man M. LY, Van T. KIM, Nhien H. LE, Na THACH, Sony T. VO, Vinh Q. NGUYEN
  • Patent number: 11004982
    Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Van H. Le, Abhishek A. Sharma, Ravi Pillarisetty, Gilbert W. Dewey, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Tahir Ghani
  • Patent number: 10998423
    Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Van H. Le, Scott B. Clendenning, Martin M. Mitan, Szuya S. Liao
  • Patent number: 10998270
    Abstract: Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Glenn A. Glass, Van H. Le, Ashish Agrawal, Benjamin Chu-Kung, Anand S. Murthy, Jack T. Kavalieros
  • Patent number: 10991802
    Abstract: Disclosed herein are quantum dot devices with gate interface materials, as well as related computing devices and methods. For example, a quantum dot device may include a quantum well stack, a gate interface material, and a high-k gate dielectric. The gate interface material may be disposed between the high-k gate dielectric and the quantum well stack.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Van H. Le, Jeanette M. Roberts, David J. Michalak, James S. Clarke, Zachary R. Yoscovits
  • Patent number: 10985263
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Dipanjan Basu, Ashish Agrawal, Van H. Le, Benjamin Chu-Kung, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani
  • Patent number: 10964820
    Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.
    Type: Grant
    Filed: December 24, 2016
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Gilbert W. Dewey, Jack T. Kavalieros
  • Patent number: 10964701
    Abstract: A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Anil Sharma, Van H. Le, Gilbert William Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
  • Patent number: 10950301
    Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Rafael Rios, Abhishek Anil Sharma, Van H. Le, Gilbert William Dewey, Jack T. Kavalieros
  • Patent number: 10950733
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 16, 2021
    Assignee: Google LLC
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Publication number: 20210074766
    Abstract: A memory device includes a first electrode, a non-volatile memory element having a first terminal and a second terminal, where the first terminal is coupled to the first electrode. The memory device further includes a selector having a first terminal, a second terminal and a sidewall between the first and second terminals, where the second terminal of the selector is coupled to the first terminal of the non-volatile memory element. A second electrode is coupled to the second terminal of the selector and a third electrode laterally adjacent to the sidewall of the selector.
    Type: Application
    Filed: September 30, 2017
    Publication date: March 11, 2021
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Willy Rachmady
  • Publication number: 20210074825
    Abstract: Disclosed herein are selector devices, and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, a selector material between the first electrode and the second electrode, and a getter layer between the first electrode and the selector material. The first electrode may include a material having a work function that is less than 4.5 electron volts.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey, Willy Rachmady
  • Publication number: 20210074702
    Abstract: A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 11, 2021
    Applicant: Intel Corporation
    Inventors: Van H. Le, Marko Radosavljevic, Han Wui Then, Willy Rachmady, Ravi Pillarisetty, Abhishek Sharma, Gilbert Dewey, Sansaptak Dasgupta
  • Patent number: 10930791
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Van H. Le, Rafael Rios, Shriram Shivaraman, Jack T. Kavalieros, Marko Radosavljevic
  • Patent number: 10930679
    Abstract: Thin film transistors (TFTs) including a channel and source/drain that comprise an oxide semiconductor. Oxide semiconductor within the source/drain may be more ordered than the oxide semiconductor within the channel. The localized increased order of the oxide semiconductor may reduce TFT access resistance while retaining good channel gating properties. In some embodiments, order within the source or drain templates from order in adjacent contact metallization. Contact metal at the interface of the oxide semiconductor may be chosen to promote grain growth in the oxide semiconductor during deposition of the oxide semiconductor, or through solid phase epitaxy of the oxide semiconductor subsequent to deposition. Where TFT circuitry is integrated into the BEOL of a CMOS FET IC fabrication process, an EOL forming gas anneal may be employed to both passivate CMOS FETs and crystalize a source/drain of the TFTs.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Abhishek A. Sharma, Shriram Shivaraman, Van H. Le, Ravi Pillarisetty, Tahir Ghani
  • Patent number: 10930766
    Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Van H. Le, Jack T. Kavalieros, Sanaz K. Gardner
  • Publication number: 20210050455
    Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.
    Type: Application
    Filed: October 19, 2020
    Publication date: February 18, 2021
    Inventors: Van H. LE, Gilbert DEWEY, Rafael RIOS, Jack T. KAVALIEROS, Marko RADOSAVLJEVIC, Kent E. MILLARD, Marc C. FRENCH, Ashish AGRAWAL, Benjamin CHU-KUNG, Ryan E. ARCH