Patents by Inventor Van H. Le

Van H. Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098931
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Abhishek SHARMA, Nazila HARATIPOUR, Seung Hoon SUNG, Benjamin CHU-KUNG, Gilbert DEWEY, Shriram SHIVARAMAN, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Matthew V. METZ, Arnab SEN GUPTA
  • Publication number: 20200098754
    Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.
    Type: Application
    Filed: June 29, 2017
    Publication date: March 26, 2020
    Inventors: Ravi PILLARISETTY, Willy RACHMADY, Marko RADOSAVLJEVIC, Van H. LE, Jack T. KAVALIEROS
  • Publication number: 20200098932
    Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Travis W. LAJOIE, Abhishek SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Juan ALZATE VINASCO
  • Publication number: 20200098875
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Seung Hoon SUNG, Justin WEBER, Matthew METZ, Arnab SEN GUPTA, Abhishek SHARMA, Benjamin CHU-KUNG, Gilbert DEWEY, Charles KUO, Nazila HARATIPOUR, Shriram SHIVARAMAN, Van H. LE, Tahir GHANI, Jack T. KAVALIEROS, Sean MA
  • Publication number: 20200098934
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, where the channel layer includes a first region and a second region, and the first region has a first dopant concentration. A gate electrode is above the first region of the channel layer and separated from the channel layer by a gate dielectric layer. A spacer is next to the gate electrode to separate the gate electrode from a drain electrode or a source electrode above the channel layer. The spacer includes a dopant material in contact with the second region of the channel layer, and the second region has a second dopant concentration different from the first dopant concentration in the first region. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Shriram SHIVARAMAN, Gilbert DEWEY, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI, Seung Hoon SUNG, Nazila HARATIPOUR, Abhishek SHARMA
  • Publication number: 20200098887
    Abstract: Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Gilbert DEWEY, Van H. LE, Abhishek SHARMA, Jack T. KAVALIEROS, Sean MA, Seung Hoon SUNG, Nazila HARATIPOUR, Tahir GHANI, Justin WEBER, Shriram SHIVARAMAN
  • Publication number: 20200098657
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Inventors: Arnab SEN GUPTA, Matthew METZ, Benjamin CHU-KUNG, Abhishek SHARMA, Van H. LE, Miriam R. RESHOTKO, Christopher J. JEZEWSKI, Ryan ARCH, Ande KITAMURA, Jack T. KAVALIEROS, Seung Hoon SUNG, Lawrence WONG, Tahir GHANI
  • Publication number: 20200098926
    Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.
    Type: Application
    Filed: September 26, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Brian S. Doyle, Elijah V. Karpov, Prashant Majhi, Gilbert W. Dewey, Benjamin Chu-Kung, Van H. Le, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20200091156
    Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 19, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-hua Wang, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Umut Arslan, Travis W. Lajoie, Chieh-jen Ku
  • Publication number: 20200091274
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a gate dielectric layer adjacent to the channel layer, and a gate electrode separated from the channel layer by the gate dielectric layer. The gate dielectric layer includes a non-linear gate dielectric material. The gate electrode, the channel layer, and the gate dielectric layer form a non-linear capacitor. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Abhishek SHARMA, Ravi PILLARISETTY, Brian DOYLE, Elijah KARPOV, Prashant MAJHI, Gilbert DEWEY, Benjamin CHU-KUNG, Van H. LE, Jack T. KAVALIEROS, Tahir GHANI
  • Patent number: 10593785
    Abstract: A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Sanaz K. Gardner, Willy Rachmady, Van H. Le, Matthew V. Metz, Seiyon Kim, Ashish Agrawal, Jack T. Kavalieros
  • Publication number: 20200083354
    Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 31, 2016
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Seung Hoon SUNG, Dipanjan BASU, Ashish AGRAWAL, Van H. LE, Benjamin CHU-KUNG, Harold W. KENNEL, Glenn A. GLASS, Anand S. MURTHY, Jack T. KAVALIEROS, Tahir GHANI
  • Publication number: 20200083225
    Abstract: Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Sean T. Ma, Aaron D. Lilak, Abhishek A. Sharma, Van H. Le, Seung Hoon Sung, Gilbert W. Dewey, Benjamin Chu-Kung, Jack T. Kavalieros, Tahir Ghani
  • Publication number: 20200083359
    Abstract: Embodiments related to transistors having one or more non-planar transition metal dichalcogenide cladding layers, integrated circuits and systems incorporating such transistors, and methods for fabricating them are discussed.
    Type: Application
    Filed: June 29, 2017
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek Sharma, Van H. Le, Gilbert Dewey, Willy Rachmady
  • Patent number: 10580882
    Abstract: Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Jack T. Kavalieros, Willy Rachmady, Matthew V. Metz, Van H. Le, Seiyon Kim, Benjamin Chu-Kung
  • Publication number: 20200066326
    Abstract: A high retention time memory element is described that has dual gate devices. In one example, the memory element has a write transistor with a metal gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.
    Type: Application
    Filed: December 23, 2015
    Publication date: February 27, 2020
    Inventors: Rafael RIOS, Gilbert DEWEY, Van H. LE, Jack KAVALIEROS, Mesut METERELLIYOZ
  • Publication number: 20200066515
    Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.
    Type: Application
    Filed: July 2, 2016
    Publication date: February 27, 2020
    Inventors: Van H. LE, Benjamin CHU-KUNG, Willy RACHMADY, Marc C. FRENCH, Seung Hoon SUNG, Jack T. KAVALIEROS, Matthew V. METZ, Ashish AGRAWAL
  • Publication number: 20200066912
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 27, 2020
    Inventors: Gilbert DEWEY, Van H. LE, Rafael RIOS, Shriram SHIVARAMAN, Jack T. KAVALIEROS, Marko RADOSAVLJEVIC
  • Publication number: 20200058705
    Abstract: Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon substrate and include a second gate, a p-type semiconducting layer over the second gate, an n-type semiconducting layer over the p-type semiconducting layer, a bit line over the n-type semiconducting layer, a first gate over the n-type semiconducting layer, and a source line over the n-type semiconducting layer. The transmission gate may be coupled to a memory element.
    Type: Application
    Filed: December 30, 2016
    Publication date: February 20, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert W. Dewey
  • Publication number: 20200058798
    Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.
    Type: Application
    Filed: December 24, 2016
    Publication date: February 20, 2020
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Van H. Le, Gilbert W. Dewey, Willy Rachmady